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(Fosc / (4 * I2C Data Rate)) 1 (4 MHz / (4 * 100 kHz)) 1 (4 x 10**6 / (4 * 100 x 10**3)) 1 10 1 9
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In a PIC microcontroller running at 4 MHz, a value of 9 must be loaded into the SSPADD to have a 100-kHz I2C data transfer.
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TABLE 16.9 BIT
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MSSP SSPCON2 BIT DEFINITION FUNCTION
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GCEN Enable interrupt when general call address (0x0000) is received. ACKSTAT Received acknowledge status; set when acknowledge was received. ACKDT Acknowledge value driven out on data write. ACKEN Acknowledge sequence enable bit, which when set will initiate an acknowledge sequence on SDA/SCL; cleared by hardware. RCEN I2C receive enable bit PEN Stop condition initiate bit; when set, stop condition on SDA/SCL; cleared by hardware. RSEN Set to initiate the repeated start condition on SDA/SCL; cleared by hardware. SEN When set, a start condition is initiated on the SDA/SCL; cleared by hardware.
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To send data from the PIC microcontroller to an I2C device using the MSSP, the following steps must be taken:
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1 The SDA/SCL lines must be put into input mode (i.e., their respective TRIS bits
must be set).
2 I2C master mode is enabled. This is accomplished by setting the SSPEN bit of
SSPCON and writing 0b01000 to the SSPM3 SSPM0 bits of the SSPCON register.
TABLE 16.10 BIT MSSP SSPSTAT BIT DEFINITION FUNCTION
7 6 5 4 3 2 1 0
SMP Set to have data sampled after active-to-idle transition; reset to sample at active-to-idle transition; not available in BSSP. CKE Set to TX data on idle-to-active transition; else TX data on active-to-idle transition; not available in BSSP. D/_A Used by I2C. P Used by I2C. S Used by I2C. R/_W Used by I2C. UA Used by I2C. BF Busy ag; reset while SPI operation active.
SERIAL I/O
PIC Micro 1 K to 10 K
I2C Devices
Device 1
Device 2
SDA SCL
Figure 16.15 Typical I2C connection to a PIC microcontroller with separate pull-up resistors.
3 A start condition is initiated by setting the SEN bit of SSPCON2. This bit is then 4
5 6 7 8 9
10 11
polled until it is reset. SSPBUF is loaded with the address of the device to access. Note that for many I2C devices, the least signi cant bit transmitted is the read/write bit. The R/_W bit of SSPSTAT is polled until it is reset (which indicates that the transmit has been completed). The ACK bit from the receiving device is checked by reading the ACKDT bit of the SSPCON2 register. SSPBUF is loaded with the rst 8 bits of data or a secondary address that is within the device being accessed. The R/_W bit of SSPSTAT is polled until it is reset. The ACK bit from the receiving device is checked by reading the ACKDT bit of the SSPCON2 register. A new start condition may have to be initiated between the rst and subsequent data bytes. This is initiated by setting the SEN bit of SSPCON2. This bit is then polled until it is reset. Operations 6 through 8 are repeated until all data is sent or a NACK (negative acknowledge) is received from the receiving device. A stop condition is initiated by setting the PEN bit of SSPCON2. This bit is then polled until it is reset.
This sequence of operations is shown in Fig. 16.16. Note that in the gure the SSPIF interrupt request ag operation is shown. In the preceding sequence, I avoid interrupts, but the SSPIF bit can be used either to request an interrupt or to avoid the need to poll different bits to wait for the various operations to complete. To receive data from a device employs a similar set of operations, with the only difference being that after the address byte(s) have been sent, the MSSP is con gured to receive data when the transfer is initiated:
1 The SDA/SCL lines must be put into input mode (i.e., their respective TRIS bits must
be set).
2 I2C master mode is enabled. This is accomplished by setting the SSPEN bit of
SSPCON and writing 0b01000 to the SSPM3 SSPM0 bits of the SSPCON register.
PIC MCU OPTIONAL HARDWARE FEATURES
MSSP I2C data address/transmission.
3 A start condition is initiated by setting the SEN bit of SSPCON2. This bit is then 4
5 6 7 8
10 11
polled until it is reset. SSPBUF is loaded with the address of the device to access. Note that for many I2C devices, the least signi cant bit transmitted is the read/write bit. The R/_W bit of SSPSTAT is polled until it is reset (which indicates that the transmit has been completed). The ACK bit from the receiving device is checked by reading the ACKDT bit of the SSPCON2 register. SSPBUF is optionally loaded with the secondary address within the device being read from. The R/_W bit of SSPSTAT is polled until it is reset. If a secondary address was written to the device being read from, reading the ACKDT bit of the SSPCON2 register checks the ACK bit from the receiving device. A new start condition may have to be initiated between the rst and subsequent data bytes. This is initiated by setting the SEN bit of SSPCON2. This bit is then polled until it is reset. If the secondary address byte was sent, then a second device address byte (with the read indicated) may have to be sent to the device being read. The R/_W bit of SSPSTAT is polled until it is reset. The ACKDT will be set (NACK) or reset (ACK) to indicate whether or not the data byte transfer is to be acknowledged in the device being read. The RCEN bit in the SSPCON2 register is set to start a data byte receive. The BF bit of the SSPSTAT register is polled until the data byte has been received.
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