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SERIAL I/O
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MSSP I2C data address/read.
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12 Operations 10 and 11 are repeated until all data is received, and a NACK (negative
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acknowledge) is sent to the device being read
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13 A stop condition is initiated by setting the PEN bit of SSPCON2. This bit is then
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polled until it is reset. Figure 16.17 show the data receive operation waveform Along with the single master mode, the MSSP is also capable of driving data in multimaster mode. In this mode, if a data write collision is detected, it stops transmitting data and requests an interrupt to indicate that there is a problem. An I2C collision is the case where the current device is transmitting a high data value, but there is a low data value on the SDA line. This condition is shown in Fig. 16.18. The WCOL bit of the SSPCON register indicates that the collision has taken place. When the collision occurs, the I2C software must wait some period of time (I use the time required to transmit 3 bytes) before polling the SDA and SCL lines to ensure that they are high and then initiating a repeated start condition operation. A repeated start condition is the process of restarting the I2C data transfer right from the beginning (even if it was halfway through when the collision occurred).
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Expected High Data Value SDA Actual Low Data Value SCL BCLIF Request Interrupt for Bus Collision
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PIC MCU OPTIONAL HARDWARE FEATURES
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Bit 0 Bit 1 Start Bit
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Bit 0 Bit 3 Bit 4 Parity Stop Bit Bit
Data
Baudot asynchronous serial data.
USART ASYNCHRONOUS SERIAL COMMUNICATIONS
The PIC microcontroller s universal asynchronous synchronous receiver transmitter (USART) hardware allows you to interface with serial devices such as a PC using RS-232 or for synchronous serial devices, with the PIC microcontroller providing the clock or having an external clock drive the data rate. The USART module is best suited for asynchronous serial data transmission, and in this section, I will be concentrating on its capabilities. Asynchronous data has been discussed elsewhere in more detail in this book. The PIC microcontroller transmits and receives NRZ (no return to zero) asynchronous data in the format shown in Fig. 16.19. The gure shows 5 bits of serial data the PIC microcontroller can transfer 8 or 9 bits although by setting the high-order bits of the output word; smaller data packets can be sent. If the USART is used for synchronous data, the bits can be latched into the destination on the failing edge of the clock. In both these cases, a byte is sent within a packet. While I have discussed packet decoding in detail elsewhere in this book, in this section I ll tend to treat the packet encoding and decoding as a black box part of the USART and deal with how the data bytes are transmitted and received. There are three modules to the USART: the clock generator, the serial data transmission unit, and the serial data reception unit. The two serial I/O units require the clock generator for shifting data out at the write interval. The clock generator s block diagram is shown in Fig. 16.20. In the clock generator circuit, the SPBRG register is used as a comparison value for the counter. When the counter is equal to the SPBRG register s value, a clock tick output is made, and the counter is reset. The counter operation is gated and controlled by the SPEN (serial port enable) bit along with the synch (which selects whether the port is in synchronous or asynchronous mode) and BRGH (which selects the data rate) bits.
SYNCH
SPEN FOsc/4
BRGH
Counter
Reset
Clock Output Receiver Sensor Clock
Comparator
A == B
SPBRG
USART clock block diagram.
SERIAL I/O
Unfortunately, in the PIC microcontroller USART, the bits used to control the operation of the clock generator, transmit unit, and receive unit are spread between the TXSTA and RCSTA registers, along with the interrupt enable and acknowledge registers. The individual bits will be de ned at the end of this section, after the three functions of the USART are explained. For asynchronous operation, the data speed is speci ed by the formula
Data Rate = Fosc / (16 x (4 ** (1 BRGH)) x (SPBRG + 1))
This formula can be rearranged so that the SPBRG value can be derived from the desired data rate:
SPBRG = Fosc / (Data Rate x 16 x (4 ** (1 - BRGH))) 1
Thus, for a PIC microcontroller running at 4 MHz, the SPBRG value for a 1,200 bps data rate with BRGH reset is calculated as
SPBRG = = = = = Fosc / (Data Rate x 16 x (4 ** (1 BRGH))) 1 4 MHz / (1200/sec x 16 (4 ** (1 0))) 1 4 (10**6) / (1200 x 16 x 4) 1 52.0833 1 51.0833
With 51 stored in SPBRG, there will be an actual data rate of 1,201.9 bps, which has an error rate of 0.16 percent to the target data rate of 1,200 bps. This error is well within limits to prevent any bits from being read in error. There is one thing that I should note about the USART clock generator, and that is that for many early PIC microcontroller part numbers, the BRGH bit does not work properly when it is set. This is not an issue with PIC microcontroller part numbers issued after 2000, but you should be aware of this if you are working with something like a PIC16C74, which was released around 1996 the USART will not work properly with the BRGH bit set. If you are working with EPROM (C technology indicator in the part number), I recommend that you always develop your applications with the BRGH bit reset. If you need data rates faster than what is possible for the PIC microcontroller clock (2,400 bps is the maximum for a 4-MHz clock), I recommend that you increase the PIC microcontroller s clock speed rather than risk setting BRGH in a device in which it may not work properly. The transmission unit of the USART can send 8 or 9 bits in a clocked (synchronous) or unclocked (synchronous) manner. The block diagram of the hardware is shown in Fig. 16.21. If the synch bit is set, then data is driven out on the PIC microcontroller s RX pin, with the data clock being either driven into or out of the TX pin. When data is loaded into the TXREG, if CSRC is reset, then an external device will clock it out. If CSRC can be shifted 8 or 9 bits at a time, with the operation stopping when the data has been shifted out. An interrupt can be requested when the operation is complete.
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