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Figure 17.41 The SPI protocol is a very typical synchronous serial protocol with a device chip select.
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SYNCHRONOUS SERIAL INTERFACES
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Figure 17.42 The input and output bits can be combined to simplify the wiring between devices.
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and DI/DO limits any current ows when both the microcontroller and the device are driving the line.
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The most popular form of microcontroller network is I2C (also known as I2C or eyesquared-cee ), which stands for inter-intercomputer communications. This standard was developed originally by Philips in the late seventies as a method to provide an interface between microprocessors and peripheral devices without wiring full address, data, and control busses between devices. I2C also allows sharing of network resources between processors (which is known as multimastering). The I2C bus consists of two lines, a clock line (SCL) that is used to strobe data (from the SDA line) from or to the master that currently has control over the bus. Both these bus lines are pulled up (to allow multiple devices to drive them). An I2C-controlled home entertainment system might be wired as in Fig. 17.43. The two bus lines are used to indicate that a data transmission is about to begin, as well as pass the data on the bus. To begin a data transfer, a master puts a start condition on the bus. Normally, when the bus is in the idle state, both the clock and the data lines are not being driven (and are
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Vcc Main Processor SCL (Clock) SDA (Data) Tape Deck CD Player I/R Remote 1 K 10 K Pull Ups
Amplifier
Tuner
Figure 17.43 The I2C protocol is designed to support multiple devices on a single network wiring.
PIC MCU INPUT AND OUTPUT DEVICE INTERFACING
Line Start Idle Cond n
Bit Xtmit
Stop Line Cond n Idle
Figure 17.44 The I2C waveforms are similar to other synchronous serial protocols.
pulled high). To initiate a data transfer, the master requesting the bus pulls down the SDA bus line, followed by the SCL bus line. During data transmission, this is an invalid condition because the data line is changing while the clock line is active/high. Each bit is then transmitted to or from the slave (the device the message is being communicated with by the master), with the negative clock edge being used to latch in the data, as shown in Fig. 17.44. To end data transmission, the reverse is executed; the clock line is allowed to go high, which is followed by the data line. Data is transmitted in a synchronous (clocked) fashion. The most signi cant bit is sent rst, and after 8 bits are sent, the master allows the data line to oat (it doesn t drive it low) while strobing the clock to allow the receiving device to pull the data line low as an acknowledgment that the data was received. After the acknowledge bit, both the clock and the data lines are pulled low in preparation for the next byte to be transmitted or a stop/start condition is put on the bus. Figure 17.45 shows the data waveform. Sometimes the acknowledge bit will be allowed to oat high, even though the data transfer has completed successfully. This is done to indicate that the data transfer has completed and the receiver (which is usually a slave device or a Master that is unable to initiate data transfer) can prepare for the next data request. There are two maximum speeds for I2C (because the clock is produced by a master, there really is no minimum speed) standard mode runs at up to 100 kbps, and fast mode
SDA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Transmitter Receiver
Ack Bit
An I2C data packet.
SYNCHRONOUS SERIAL INTERFACES
Std. Fast SCL
4.0 0.6
4.7 1.3
4.0 0.6
4.0 0.6
4.7 1.4 Stop Line Cond n Idle
Start Bit Cond n Xtmit All Times are Minimum Values All Times in u Seconds
Bit timing for I2C data.
can transfer data at up to 400 kbps. Figure 17.46 shows the timing speci cations for both the standard ( std. or 100-kHz data rate) and fast (400-kHz data rate). A command is sent from the master to the receiver in the format shown in Fig. 17.47. The receiver address is 7 bits long and is the bus address of the receiver. There is a loose standard to use the most signi cant 4 bits to identify the type of device, whereas the next 3 bits are used to specify one of eight devices of this type (or further specify the device type). As I just said, this is loose standard. Some devices require certain patterns for the second 3 bits, whereas others (such as some large serial EEPROMS) use these bits to specify an address inside the device. In addition, there is a 10-bit address standard in which the rst 4 bits are all set, the next bit reset, and the last 2 bits are the most signi cant 2 bits of the address, with the nal 8 bits being sent in a following byte. All this means is that it is very important to map out the devices to be put on the bus and all their addresses. This is really all there is to I2C communication, except for a few points. In some devices, a start bit has to be resent to reset the receiving device for the next command (i.e., in a serial EEPROM read, the rst command sends the address to read from and the second reads the data at that address).
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