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0010 01da ffff ffff
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Add w register to the contents of Reg and C, store the result according to d result in w register; if a is set, then Reg is in the BSR bank, else Reg is in the access bank
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addwfc Reg, d,a
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if ( d == 1) wreg = wreg + Reg + C else Reg = wreg + Reg + C endif if (((wreg > 0) & (Reg > 0)) & ((wreg + Reg + C) > 0x07F)) OV = 1 else OV = 0 endif if ((wreg + Reg + C) & 0x080) != 0) N = 1 else N = 0 endif if ((wreg + Reg + C) > 0x0FF) C = 1 else C = 0 endif if (((wreg & 0x0F) + Reg & 0x0F) + C) > 0x0F) DC = 1 else DC = 0 endif if (((wreg + Reg + C) & 0x0FF) == 0x000) Z = 1 else Z = 0 endif
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(Continued )
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TABLE B.6 INSTRUCTION
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PIC18C INSTRUCTION SET (CONTINUED) FORMAT OPERATION BIT PATTERN
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AND a constant to the w register and store the result in the w register
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andlw Constant
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wreg = wreg & Constant if ((wreg & Constant) == 0x000) Z = 1 else Z = 0 endif if ((wreg & Constant) & 0x080) != 0) N = 1 else N = 0 endif if ( d == 1) wreg = wreg & Reg else Reg = wreg & Reg endif if ((wreg & Reg) = 0x000) Z = 1 else Z = 0 endif if ((wreg & Reg) & 0x080) != 0) N = 1 else N = 0 Endif
0000 1011 kkkk kkkk
AND w register to the contents of Reg and store the result according to d result in w register; if a is set, then Reg is in the BSR bank, else it is in the access bank
andwf Reg, d, a
0001 01da ffff ffff
Branch if the carry ag is set; label is a two s complement offset; one instruction cycle if branch not executed, two if branch executed Clear the speci ed bit in Reg; if a is set, then Reg is in the BSR bank, else Reg is in the access bank Branch if negative ag is set; label is a two s complement offset; one instruction cycle if branch not executed, two if branch executed Branch if the carry ag is reset; label is a two s complement offset; one instruction cycle if branch not executed, two if branch executed Branch if negative ag is reset; label is a two s complement offset; one instruction cycle if branch not executed, two if branch executed Branch if over ow ag is reset; label is a two s complement offset; one instruction cycle if branch not executed, two if branch executed Branch if the zero ag is reset; label is a two s complement offset; one instruction cycle if branch not executed, two if branch executed Branch if over ow ag is set; label is a two s complement offset; one instruction cycle if branch not executed, two if branch executed
bc Label
if (C == 1) PC = PC + 2 + Label endif Reg = Reg & (0x0FF ^ 1 << Bit))
1110 0010 kkkk kkkk
bcf Reg, Bit, a
1001 bbba ffff ffff
bn Label
if (N == 1) PC = PC + 2 + Label endif if (C == 0) PC = PC + 2 + Label endif if (N == 0) PC = PC + 2 + Label endif if (OV == 0) PC = PC + 2 + Label endif if (Z == 0) PC = PC + 2 + Label endif if (OV == 1) PC = PC + 2 + Label endif
1110 0110 kkkk kkkk
bnc Label
1110 0011 kkkk kkkk
bnn Label
1110 0111 kkkk kkkk
bnov Label
1110 0101 kkkk kkkk
bnz Label
1110 0001 kkkk kkkk
bov Label
1110 0100 kkkk kkkk
(Continued )
TABLE B.6 INSTRUCTION
PIC18C INSTRUCTION SET (CONTINUED) FORMAT OPERATION BIT PATTERN
Branch always; label is a two s complement offset; two instruction cycles Set the speci ed bit in Reg; if a is set, then Reg is in the BSR bank, else Reg is in the access bank Test the speci ed bit in Reg and skip if clear; if a is set, then the BSR is used for Reg, else the access bank is used; one instruction cycle if skip not executed, two if skip executed Test the speci ed bit in Reg and skip if set; if a is set, then the BSR is used for Reg, else the access bank is used; one instruction cycle if skip not executed, two if skip executed. Toggle the speci ed bit in Reg; if a is set, then the BSR is used for Reg, else the access bank is used Branch if the zero ag is set; label is two s complement offset; one instruction cycle if branch not executed, two if branch executed Call the 20-bit label address; if s is set, save the context registers (two instruction cycles)
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