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PIC MICROCONTROLLER SUMMARY
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TABLE B.8 ADDRESS
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LOW-END PIC MICROCONTROLLER REGISTER DEFINITIONS (CONTINUED) REGISTER BITS BIT FUNCTION
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WDT rate: 64:1 32:1 16:1 8:1 4:1 2:1 1:1
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The STATUS register in mid-range PIC microcontroller is de ned as listed in Table B.10. The OPTION register (which has the label OPTION_REG in the Microchip include les) is de ned in Table B.11. Many devices have the PCON register (see Table B.12) that enhances the returned information contained in the _TO and _PD bits of the STATUS register. The PCLATH register s contents (see Table B.13) are written to the program counter each time a goto or call instruction is executed or if the contents of PCL are changed. Some mid-range devices are now available with built-in RC oscillators. To make the operation of the oscillators more accurate, the OSCCAL register is written to with a factory-speci ed calibration value register as presented in Table B.14.
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TABLE B.9 OFFSET
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0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B
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INDF TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD PORTE PCLATH INTCON
INDF OPTION PCL STATUS FSR TRISA TRISB TRISC TRISD TRISE PCLATH INTCON Available in 28/40-pin parts Available in 40-pin parts Available in 40-pin parts
APPENDIX B
TABLE B.10 BIT
MID-RANGE STATUS REGISTER DEFINITION FUNCTION
7 6 5 4 3 2 1 0
IRP FSR select between the high and low register banks RP1 RP0 direct addressing select banks (0 3) _TO Time-out bit; reset after a watchdog timer reset _PD Power-down active bit; reset after sleep instruction Z set when the 8-bit result is equal to zero DC set when the low nybble of addition/subtraction result carries to the high nybble C set when the addition/subtraction result carries to the next byte; also used with the rotate instructions
TABLE B.11 BIT
MID-RANGE OPTION REGISTER DEFINITION FUNCTION
7 6 5 4 3 2 0
_RBPU when reset, the PORTB pin pull-up is enabled. INTEDG when set, interrupt request on rising edge of RB0/INT pin. T0CS when set, TMR0 is incremented from the T0CKI pin, else by the internal instruction clock. T0SE when set, TMR0 is incremented on the high to low (falling edge) of T0CKI. PSA prescaler assignment bit; when set, the prescaler is assigned to the watchdog timer, else to TMR0. PS2 PS0 prescaler rate select. Bit 111 110 101 000 011 010 001 000 TMR0 Rate 256:1 128:1 64:1 32:1 16:1 8:1 4:1 2:1 WDT Rate 128:1 64:1 32:1 16:1 8:1 4:1 2:1 1:1
PIC MICROCONTROLLER SUMMARY
TABLE B.12 BIT
MID-RANGE PCON REGISTER DEFINITION FUNCTION
7 6 3 2 1 0
MPEEN set if there is a memory parity error; this capability is built into a small number of PIC microcontrollers. Unused _PER reset when there was a program memory parity error; this capability is built into a small number of PIC microcontrollers. _POR reset when execution is from a power-on reset. _BOR reset when execution is from a brown-out reset.
Interrupts are controlled from the INTCON register (see Table B.15), which controls the basic mid-range PIC microcontroller interrupts as well as access to enhanced interrupt features. Bit 6 of INTCON may be a peripheral device interrupt enable/request bit, or it can be PEIE, which when set will enable peripheral interrupts set in the PIR and PIE registers. The PIR register(s) contains the F bits (interrupt request active), whereas PIE contains the E bits (interrupt request enable). As I work through the different peripherals, the E and F bits will be listed, but their actual location is part number speci c, and the datasheet will have to be consulted. Data EEPROM is accessed via the EEADR and EEDATA registers, with EECON1 (see Table B.16) and EECON2 providing the access control. EECON2 is a pseudoregister, and the act of writing to it is used to verify that the operation request is valid. The data EEPROM write interrupt request bit (EEIE) is either in a PIE register or INTCON. The parallel slave port (PSP; available only in 40-pin mid-range PIC microcontrollers and listed in Table B.17) is enabled by setting the PSPMODE bit. Interrupt request are enabled by the PSPIE ag and requested by the PSPIF ag of the PIE and PIR registers, respectively. The parallel slave port is controlled from TRISE. Note that when the parallel slave port is enabled, PORTD and PORTE cannot be used for I/O.
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