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Drawer QR Code ISO/IEC18004 in Software B.23 BIT

TABLE B.23 BIT
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MID-RANGE MSSP SSPCON1 REGISTER DEFINITION FUNCTION
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7 6 5 4 3 0
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WCOL set if SSPBUF was written to while transmitting data or not in correct mode for transmit. SSPOV set when SSP receive over ow occurs. SSPEN enables pins for SSP mode. CKP in SPI, set for idle clock high; in I2C mode, set to enable clock. SSPM3 SSPM0 SSP mode select. 1xx1 Reserved 1x1x Reserved 1000 I2C master mode, clock = Fosc/[4 * (SSPADD + 1)] 0111 I2C slave mode, 10-bit address 0110 I2C slave mode, 7-bit address 0101 SSP slave, _SS disabled.
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APPENDIX B
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TABLE B.24 BIT
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MID-RANGE MSSP SSPCON2 REGISTER DEFINITION FUNCTION
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7 6 5 4 3 2 1 0
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GCEN set to enable interrupt when general call address is received. ACKSTAT set when acknowledge received from I2C slave device. ACKDT reset to send acknowledge at the end of a byte receive. ACKEN acknowledge I2C sequence when set. RCEN set to enable I2C receive mode. PEN reset to initiate stop condition on I2C clock and data. RSEN set to initiate repeated start condition on I2C clock and data. SEN set to initiate start condition on I2C clock and data.
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TABLE B.25 BIT
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MID-RANGE MSSP SSPSTAT REGISTER DEFINITION FUNCTION
7 6 5 4 3 2 1 0
SMP data sampled at end of data output time if set, else middle. CKE data transmitted on rising edge of SCK when set. D/_A used by I2C; when set, indicates last byte transferred was data; when reset, indicates last byte transferred was address. P set when stop bit detected. S set when start bit indicated. R/_W set when command received was a read. UA set when application must update SSPADD register. BF set when buffer is full in RX and when TX is in pr.
TABLE B.26 BIT
MID-RANGE RCSTA REGISTER DEFINITION FUNCTION
7 6 5 4 3 2 1 0
SPEN set to enable the USART. RX9 set to enable 9-bit serial reception. SREN set to enable single receive for synchronous mode. CREN set to enable continuous receive mode. ADDEN enables address detection in asynchronous mode. FERR framing error bit. OERR set after overrun error. RX9D ninth bit of data received.
PIC MICROCONTROLLER SUMMARY
TABLE B.27 BIT
MID-RANGE TXSTA REGISTER DEFINITION
FUNCTION
7 6 5 4 3 2 1 0
CSRC set for synchronous clock generated internally. TX9 set to enable 9-bit data transmission TXEN set to enable transmit. SYNC set to select synchronous mode. Unused. BRGH Set to Select the High Baud Rate TRMT set when transmit shift register is empty. TX9D Ninth bit of transmit data.
For more advanced 18-pin PIC microcontrollers, ADCON1 is de ned as shown in Table B.33. Both 28- and 40-pin PIC microcontrollers have the ADCON1 register, as de ned in Table B.34. The result of the ADC operation is stored in ADRES, and ADIF is set on completion of the ADC operation to request an interrupt if ADIE is set. Moreover, 10-bit ADCs are also available in the PIC microcontroller, with a different ADCON1 register (see Table B.35). In the case of 10-bit ADCs, the result is stored in ADRESL and ADRESH. This mid-range register list does not include the PIC16C92x s LED control registers. This, as well as any other I/O hardware registers that were not available when this appendix was written, can be found in the Microchip datasheets.
TABLE B.28 BIT
MID-RANGE VRCON REGISTER DEFINITION FUNCTION
7 6 5 4 3 0
VREN set to turn on voltage reference circuit VROE set to output voltage reference externally. VRR set for low-voltage reference range; reset for high-voltage reference range. Unused. VR3 VR0 Select the reference voltage output
APPENDIX B
TABLE B.29 VR3:VR0
VRCON VALUES TO VOLTAGE OUTPUT VRR = 1 VRR = 0
1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 0011 0010 0001 0000
3.13 V 2.92 V 2.71 V 2.50 V 2.29 V 2.08 V 1.88 V 1.67 V 1.46 V 1.25 V 1.04 V 0.83 V 0.63 V 0.42 V 0.21 V 0.00 V
3.59 V 3.44 V 3.28 V 3.13 V 2.97 V 2.81 V 2.66 V 2.50 V 2.34 V 3.19 V 2.03 V 1.88 V 1.72 V 1.56 V 1.41 V 1.25 V
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