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PORTC read/write registers; I/O pins have Schmidt-trigger inputs; pin options are as follows: Bit 7 6 5 4 3 2 0 Function UART receive pin UART transmit pin Synchronous serial port data SPI data or I2C data SPI clock or I2C clock CCP1 I/O and PWM output/TMR1 clock output TMR1 clock input (Continued )
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TABLE B.36 ADDRESS
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PIC18 REGISTER DEFINITION (CONTINUED) REGISTER FUNCTION/BIT DEFINITION
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PORTD PORTE
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PORTD only available on 40-pin PIC18 devices; Schmidt-trigger inputs; used for data slave port. PORTE only available on 40-pin PIC18; Schmidt-trigger inputs for I/O mode; used for data slave port as follows: Bit 7 3 2 1 0 Function Unused Negative active chip select Negative active write enable to PIC18Cxx Negative active output enable (_RD) from PIC18Cxx
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LATA LATB LATC LATD LATE TRISA TRISB TRISC TRISD TRISE
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Data output latch/bypassing PORTA Data output latch/bypassing PORTB Data output latch/bypassing PORTC Data output latch/bypassing PORTD; only available on 40-pin PIC18 Data output latch/bypassing PORTE; only available on 40-pin PIC18 I/O pin tristate control register; set bit to 0 for output mode. I/O pin tristate control register; set bit to 0 for output mode. I/O pin tristate control register; set bit to 0 for output mode. I/O pin tristate control register; only available on 40-pin PIC18; set bit to 0 for output mode. I/O pin tristate control register; only available on 40-pin PIC18; set bit to 0 for output mode; special function bits speci ed as follows; Bit 7 6 Function IBF set when PSP is enabled and a byte has been written to the PIC microcontroller OBF set when PSP is enabled and a byte output has not been read from the chip
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5 4 3 2 1 0 0x0#9D PIE1
IBOV set when PSP is enabled and the byte written has been overwritten by a subsequent byte PSPMODE set to enable PIC microcontroller s PSP I/O port Unused TRISE2 TRIS bit for RE2 TRISE1 TRIS bit for RE1 TRISE0 TRIS bit for RE0
Peripheral interrupt enable register: Bit 7 6 5 4 3 2 1 0 Function PSPIE set to enable PSP interrupt request on read/write ADIE set to enable interrupt request on completion of A/D operation RCIE set to enable interrupt request on USART data receive TXIE set to enable interrupt request on USART transmit holding register empty SSPIE master synchronous serial port interrupt enable bit CCP1IE set to enable CCP1 interrupt request enable TMR2IE TMR2 to PR2 match interrupt request enable TMR1IE TMR1 over ow interrupt request enable
0x0#9E
PIR1
Peripheral interrupt request register: Bit 7 6 5 4 3 2 1 0 Function PSPIF set on PSP read/write ADIF set when A/D complete RCIF set on USART data receive TXIF set on USART transmit holding register empty SSPIF set on synchronous serial port data transmission/ reception complete CCP1IF set on TMR1 capture or compare match TMR2IF set on TMR2 to PR2 match TMR1IF set on TMR1 over ow (Continued )
TABLE B.36 ADDRESS
PIC18 REGISTER DEFINITION (CONTINUED) REGISTER FUNCTION/BIT DEFINITION
0x0#9F
IPR1
Peripheral interrupt priority register: Bit 7 6 5 4 3 2 1 0 Function PSPIP set to give PSP interrupt request on read/write priority ADIP set to give interrupt request on completion of A/D operation priority RCIP set to give interrupt request on USART data receive priority TXIP set to enable interrupt request on USART transmit holding register empty priority SSPIP master synchronous serial port interrupt priority when set CCP1IP set to give CCP1 interrupt request priority TMR2IP TMR2 to PR2 match interrupt request priority when set TMR1IF TMR1 over ow interrupt request priority when set
0x0#9A
PIE2
Peripheral interrupt enable register: Bit 7 4 3 2 1 0 Function Unused BCLIE bus collision interrupt request enabled when set LVDIE low-voltage detect interrupt request enabled when set TMR3IE TMR3 over ow interrupt request enabled when set CCP2IE CCP2 interrupt request enabled when set Peripheral interrupt request register: Bit 7 4 3 2 1 0 Function Unused BCLIF set for bus collision interrupt request LVDIF set for low-voltage detect interrupt request TMR3IF set for TMR3 over ow interrupt request CCP2IF set for CCP2 interrupt request
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