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0x0#9C
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Peripheral interrupt priority register: Bit 7 4 3 2 1 0 Function Unused BCLIF set for bus collision interrupt given priority LVDIF set for low-voltage detect interrupt given priority TMR3IF set for TMR3 over ow interrupt request given priority CCP2IF set for CCP2 interrupt request given priority
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USART receive status and control register: Bit 7 6 5 4 3 2 1 0 Function SPEN set to enable the USART RX9 set to enable 9-bit serial reception SREN set to enable single receive for synchronous mode CREN set to enable continuous receive mode ADDEN enables address detection in asynchronous mode FERR framing error bit OERR set after overrun error RX9D ninth bit of data received
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USART transmit status and control register: Bit 7 6 5 4 3 2 1 0 Function CSRC set for synchronous clock generated internally TX9 set to enable 9-bit data transmission TXEN set to enable transmit SYNC set to select synchronous mode Unused BRGH set to select the high baud rate TRMT set when transmit shift register is empty TX9D ninth bit of transmit data
0x0#AD 0x0#AE
TXREG RCREG SPBRG
USART transmit buffer register USART receive holding register USART clock divisor register (Continued )
0x0#AF
TABLE B.36 ADDRESS
PIC18 REGISTER DEFINITION (CONTINUED) REGISTER FUNCTION/BIT DEFINITION
0x0#B1
T3CON
TMR3 control register: Bit 7 6 3 Function RD16 enable read/write of TMR3 as a 16-bit operation T3CCP2 T3CCP2 TMR3 and TMR1 to CCPx enable bits 1x TMR3 is CCP clock source 01 TMR3 is CCP2 clock source/TMR1 is CCP1 clock source 00 TMR1 is CCP clock source T3CKPS1 T3CKPS0 TMR3 input clock Prescaler Control 11 1:8 prescaler 10 1:4 prescaler 01 1:2 prescaler 00 1:1 prescaler _T3SYNC when reset, TMR3 external clock is synchronized TMR3CS set to select external clock for TMR3; reset to select instruction clock TMR3ON set to enable TMR3
2 1 0 0x0#B2 0x0#B3 0x0#BA TMR3L TMR3H CCP2CON
Low byte of TMR3 High byte of TMR3 CCP2 control register: Bit 7 6 5 4 3 0 Function Unused DC2BX1 DC2BX0 two least signi cant bits for the 10-bit PWM CCP2M3 CCP2M0 CCP2 mode select bits: 11xx PWM mode 1011 trigger special event compare mode 1010 generate interrupt on compare match 1001 initialize CCP2 high and force low on compare match 1000 initialize CCP1 high and force high on compare match
0111 capture on every 16th rising edge 0110 capture on every 4th rising edge 0101 capture on every rising edge 0100 capture on every falling edge 0011 reserved 0010 toggle output on compare match 0001 reserved 0000 capture/compare/PWM off 0x0#BB 0x0#BC 0x0#BD CCPR2L CCPR2H CCP1CON Least signi cant capture/compare/PWM2 register Most signi cant capture/compare/PWM2 register CCP1 control register: Bit 7 6 5 4 3 0 Function Unused DC1BX1 DC1BX0 two least signi cant bits for the 10-bit PWM CCP1M3 CCP1M0 CCP1 mode select bits: 11xx PWM mode 1011 trigger special event compare mode 1010 generate interrupt on compare match 1001 initialize CCP2 high and force low on compare match 1000 initialize CCP1 high and force high on compare match 0111 capture on every 16th rising edge 0110 capture on every 4th rising edge 0101 capture on every rising edge 0100 capture on every falling edge 0011 reserved 0010 toggle output on compare match 0001 reserved 0000 capture/compare/PWM off
0x0#BE 0x0#BF
CCPR1L CCPR1H
Least signi cant capture/compare/PWM1 register Most signi cant capture/compare/PWM1 register (Continued )
TABLE B.36 ADDRESS
PIC18 REGISTER DEFINITION (CONTINUED) REGISTER FUNCTION/BIT DEFINITION
0x0#C1
ADCON1
A/D control register1: Bit 7 6 5 4 3 0 Bit 1111 1110 1101 1100 1011 1010 1001 1000 011x 0101 0100 0011 0010 0001 0000 Function ADFM set to return result in right-justi ed format; reset to return result in left-justi ed format ADCS2 upper bit of A/D conversion clock select; see ADCON0 for bit de nition Unused PCFG3 PCFG0 A/D pin con guration select bits: AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VR+ VR D D D D D D D A D D D D D A A D D D D D D D A D D D D D A A D D D D A A A A D D D D D A A D D D A A A A A D D D D A A A VR+ D VR+ VR+ VR+ VR+ A VR+ D VR+ A VR+ A VR+ A VR D D D VR A VR A VR A A A A A VR A D D D A D A A A A A A A A A A A A A A A A A D A A A A A A AN3 Vdd AN3 AN3 AN3 AN3 Vdd AN3 N/A AN3 Vdd AN3 Vdd AN3 Vdd AN2 Vss AN2 AN2 AN2 Vss Vss AN2 N/A Vss Vss Vss Vss Vss Vss
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