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ADCON0
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A/D control register2: Bit 7 6 Function ADCS1 ADCS0 ADC conversion clock select, with ADCS2 from ADCON1: 111 iInternal RC oscillator 110 divide PIC microcontroller clock by 64
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101 divide PIC microcontroller clock by 16 100 divide PIC microcontroller clock by 4 011 internal RC oscillator 010 divide PIC microcontroller clock by 32 001 divide PIC microcontroller clock by 8 000 divide PIC microcontroller clock by 2 CHS2 CHS0 ADC conversion channel: Select Bits 111 AN7 110 AN6 101 AN5 100 AN4 011 AN3 010 AN2 001 AN1 000 AN0
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2 1 0 0x0#C3 0x0#C4 0x0#C5 ADRESL ADRESH SSPCON2
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GO/_DONE set to start A/D conversion; reset by hardware when conversion before Unused ADON set to turn on the ADC function
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Low byte of the ADC result High byte of the ADC result MSSP control register2: Bit 7 6 5 4 3 2 Function GCEN set to enable interrupt when general call address is received ACKSTAT set when acknowledge received from I2C slave device ACKDT reset to send acknowledge at the end of a byte receive ACKEN acknowledge I2C sequence when set RCEN set to enable I2C receive mode PEN reset to initiate stop condition on I2C clock and data (Continued )
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TABLE B.36 ADDRESS
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PIC18 REGISTER DEFINITION (CONTINUED) REGISTER FUNCTION/BIT DEFINITION
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1 0 0x0#C6 SSPCON1
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RSEN set to initiate repeated start condition on I2C clock and data SEN set to initiate start condition on I2C clock and data
MSSP control register1: Bit 7 6 5 4 3 0 Function WCOL set if SSPBUF was written to while transmitting data or not in correct mode for transmit SSPOV set when SSP receive over ow occurs SSPEN enables pins for SSP mode CKP in SPI, set for idle clock high; in I2C mode, set to enable clock SSPM3 SSPM0 SSP mode select: 1111 I2C slave mode, 10-bit address 1110 I2C slave mode, 7-bit address 110x reserved 1011 I2C rmware-controlled master 1010 reserved 1001 reserved 1000 I2C master, Fosc/[4 * (SSPAD + 1)] 0111 I2C slave mode, 10-bit address 0110 I2C slave mode, 7-bit address 0101 SSP slave, _SS disabled 0100 SSP slave, _SS enabled 0011 SPI master, clock = TMR2 0010 SPI master, Fosc/64 0001 SPI master, Fosc/16 0000 SPI master, Fosc/4
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SSPSTAT
MSSP status register:
Bit 7 6 5 4 3 2 1 0 0x0#C8 0x0#C9 0x0#CA SSPADD SSPBUF T2CON
Function SMP data sampled at end of data output time if set, else middle CKE data transmitted on rising edge of SCK when set D/_A when set, indicates last byte transferred was data; when reset, indicates last byte transferred was address P set when stop bit detected S set when start bit indicated R/_W set when command received was a read UA set when application must update SSPADD register BF set when buffer is full in RX and when TX is in process
MSSP address compare register MSSP data buffer TMR2 control register: Bit 7 6 3 Function Unused TOUTPS3 TOUTPS0 TMR2 output postscaler: 1111 16x 1110 15x 1101 14x 1100 13x 1011 12x 1010 11x 1001 10x 1000 9x 0111 8x 0110 7x 0101 6x 0100 5x 0011 4x 0010 3x 0001 2x 0000 1x (Continued )
TABLE B.36 ADDRESS
PIC18 REGISTER DEFINITION (CONTINUED) REGISTER FUNCTION/BIT DEFINITION
2 1 0
TMR2ON set to enable TMR2 T2CKPS1 T2CKPS0 TMR2 prescaler select bits: 1x prescaler is 16 01 prescaler is 4 00 prescaler is 1
0x0#CB 0x0#CC 0x0#CD
PR2 TMR2 T1CON
TMR2 period compare register TMR2 register TMR1 control register: Bit 7 6 5 4 Function RD16 when set, enables 16-bit TMR1 operations Unused T1CKPS1 T1CKPS0 TMR1 input clock Prescaler Select 11 1:8 prescaler 10 1:4 prescaler 01 1:2 prescaler 00 1:1 prescaler T1OSCEN set to enable TMR1 oscillator _T1SYNC set to synchronize external clock input TMR1CS TMR1 clock source select; set to select external clock TMR1ON set to enable TMR1
3 2 1 0 0x0#CE 0x0#CF 0x0#D0 TMR1L TMR1H RCON
Low byte of TMR1 High byte of TMR1 Power-up status register Bit 7 6 Function IPEN set to enable priority levels on interrupts LWRT set to enable tblwt instruction to internal memory
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