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(00) Key (U1 U2) S1 S2 S3 (00) 0 0 0 (11) 1 0 0 (00) 0 0 0 (01) 0 1 0 (11) 1 0 0 (10) 1 1 0 (00) Data in 0 0 0 (00) (11) 0 0 1 (01) 0 1 0 (00) 1 0 1 (11) 1 0 0 (10) 0 1 1 (10) 1 1 0 (01) 1 1 1 0 0 0 (11) 1 0 0 (01) 0 1 0 (10) 1 1 0 (11) 0 0 1 (00) 1 0 1 (10) 0 1 1 (01) 1 1 1
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0 0 0 (11) 1 0 0 (01) 0 1 0 (10) 1 1 0 (11) 0 0 1 (00) 1 0 1 (10) 0 1 1 (01) 1 1 1
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The tree diagram for the rate 1/2 convolutional encoder.
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intended, it takes the lower branch, and then it can match all the following pairs with the branches in the decoding tree. On the basis of maximum likelihood, this would be the preferred path, and the correct input 1001 would be deduced.
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The CDV-10MIC is a single integrated circuit which implements all the functions required for a constraint length 7, rate 1/2, and punctured 2/3 or 3/4 rate, convolutional encoder, and Viterbi algorithm decoder. Important features of this chip are: Full decoder and encoder implementation for rates 1/2, 2/3, and 3/4 Complies with INTELSAT IESS-308 and IESS-309 specifications Extremely low implementation margin No external components required for punctured code implementation Operates at all information rates up to 10 Mbits/s. Higher speed versions are under development All synchronization circuits are included on chip. External connection of ambiguity state counter and ambiguity resolution inputs allows maximum application flexibility Advanced synchronization detectors enable very rapid synchronization. Rate, 3/4 block and phase synchronization in less than 8200 information bits (5500 transmitted symbols). Soft decision decoder inputs (3 bits, 8 levels) Erasure inputs for implementing punctured codes at other rates Path memory length options to optimize performance when implementing highrate punctured codes Error-monitoring facilities included on chip Synchronization detector outputs and control inputs to enable efficient synchronization in higher-speed multiplexed structures.
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Specifications for a single-chip Viterbi codec. (Courtesy of Signal Processors, Ltd., Cambridge U.K.)
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Decoding is a more difficult problem than encoding, and as the example suggests, the search process could quickly become impracticable for long messages. The Viterbi algorithm is used widely in practice for decoding. An example of a commercially available codec is the CDV10MIC single-chip codec made by Signal Processors Limited, Cambridge, U.K. The data sheet for this codec is shown in Fig. 11.4. The CDV-10MIC utilizes Viterbi decoding. It has a constraint length of 7 and can be adjusted for code rates of 1/2, 2/3, and 3/4 by means of what is termed punctured coding. With punctured coding, the basic code is generated at code rate 1/2, but by selectively discarding some of the output bits, other rates can be achieved (Mead, 2000). The advantage is that a single encoder can be used for different rates.
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11.5 Interleaving The idea behind interleaving is to change the order in which the bits are encoded so that a burst of errors gets dispersed across a number of codewords rather than being concentrated in one codeword. Interleaving as applied in block codes will be used here to illustrate
Error Control Coding
. . .
b3 Time
. . .
. . .
Column No. 1 Row No. 1 2 3 4 5 6 7 b24 b18 b12 b6 c1 c2 c3 b23 b17 b11 b5 c4 c5 c6
3 b22 b16 b10 b4 c7 c8 c9
4 b21 b15 b9 b3 c10 c11 c12
5 b20 b14 b8 b2 c13 c14 c15
6 b19 b13 b7 b1 c16 c17 b18
Row 7
Row 6
Row 5
Row 4 b1 b2 b3 b4 b5 b6
Row 3
Row 2
Row 1
Time
(c) Figure 11.5
Illustrating interleaving (see Sec. 11.5).
the technique, but it also can be used with convolutional coding (Taub and Schilling, 1986). Figure 11.5a shows part of the data bit stream where for definiteness the bits are labeled from b1 to b24. These are fed into shift registers as shown in Fig. 11.5b, where, again, for definiteness seven rows and six columns are shown. Rather than encoding the rows, the columns are encoded so that the parity bits fill up the last three rows. It will be seen, therefore, that the bits are not encoded in the order in which they appear in the data bit stream. The encoded bits are read out row by row as shown in Fig. 11.5c. Row 4 is shown in detail. If now an error burst occurs which changes bits b5, b4, and b3, these will appear as separate errors in the encoded words formed by columns 2, 3, and 4. The words formed by the column bits are encoded to correct single errors (in this example), and therefore, the burst of errors has been corrected.
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