ssrs barcode image PN binary sequence. One element is known as a chip. in Software

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PN binary sequence. One element is known as a chip.
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14.10.1 Direct-sequence spread spectrum
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In Fig. 14.33, p(t) is an NRZ binary information signal, and c(t) is a NRZ binary code signal. These two signals form the inputs to a multiplier (balanced modulator), the output of which is proportional to the product p(t)c(t). This product signal is applied to a second balanced modulator, the output of which is a BPSK signal at the carrier frequency. For clarity, it is assumed that the carrier is the uplink frequency, and hence the uplink carrier is described by eU(t) c(t)p(t) cos
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(14.33)
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The corresponding downlink carrier is eD(t) c(t)p(t) cos
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(14.34)
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At the receiver, an identical c(t) generator is synchronized to the c(t) of the downlink carrier. This synchronization is carried out in the acquisition and tracking block. With c(t) a polar NRZ type waveform, and with the locally generated c(t) exactly in synchronism with the transmitted c(t), the product c2(t) 1. Thus the output from the multiplier is c(t)eD(t) c2(t)p(t) cos p(t) cos Dt
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(14.35)
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This is identical to the conventional BPSK signal given by Eq. (10.14), and hence detection proceeds in the normal manner.
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14.10.2 The code signal c(t)
The code signal c(t) carries a binary code that has special properties needed for successful implementation of CDMA. The binary symbols used in the codes are referred to as chips rather than bits to avoid confusion
c(t)p(t)cos
c(t)p(t)cos
p(t) Tx Rx Acquisition and Tracking
p(t)cos
To coherent detector c(t)
c(t)
A basic CDMA system.
Fourteen
with the information bits that will also be present. Chip generation is controlled by a clock, and the chip rate, in chips per second, is given by the clock speed. Denoting the clock speed by Rch, the chip period is the reciprocal of the clock speed: Tch 1 Rch (14.36)
The waveform c(t) is periodic, in that each period is a repetition of a given sequence of N chips. The sequence itself exhibits random properties, which will be described shortly. The periodic time for the waveform is TN NTch (14.37)
The codes are generated using binary shift registers and associated linear logic circuits. The circuit for a three-stage shift register that generates a sequence of N 7 chips is shown in Fig. 14.34a. Feedback occurs from stages 1 and 3 as inputs to the exclusive OR gate. This provides the input to the shift register, and the chips are clocked through at the clock rate Rch. The generator starts with all stages holding binary 1s, and the following states are as shown in the table in Fig. 14.34. Stage 3 also provides the binary output sequence. The code waveform generated from this code is shown in Fig. 14.34b.
Clock 1 2 3 V t (b) 2 1 1 0 1 0 0 1 1 1 3 1 1 1 0 1 0 0 1 1 Repeat (a)
1 1 0 1 0 0 1 1 1 0
Generation of a 7-chip maximal sequence code.
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Such codes are known as maximal sequence or m-sequence codes because they utilize the maximum length sequence that can be generated. For Fig. 14.34a the maximum length sequence is 7 chips as shown. In general, the shift register passes through all states (all combinations of 1s and 0s in the register) except the all-zero state when generating a maximal sequence code. Therefore, a code generator employing an n-stage shift register can generate a maximum sequence of N chips, where N 2n 1 (14.38)
The binary 1s and 0s are randomly distributed such that the code exhibits noiselike properties. However, there are certain deterministic features described below, and the codes are more generally known as PN codes, which stands for pseudo-noise codes. 1. The number of binary 1s is given by No. of 1s 2 2
(14.39)
and the number of binary 0s is given by No. of 0s 2 2
(14.40)
The importance of this relationship is that when the code uses V volts for a binary 1 and V volts for a binary 0, the dc offset is close to zero. Since there is always one more positive chip than negative, the dc offset will be given by dc offset V N (14.41)
The dc offset determines the carrier level relative to the peak value; that is, the carrier is suppressed by amount 1/N for BPSK. For example, using a code with n 8 with BPSK modulation, the carrier will be suppressed by 1/255 or 48 dB. 2. The total number of maximal sequences that can be generated by an n-stage shift register (and its associated logic circuits) is given by Smax (N ) n (14.42)
Here, (N ) is known as Euler s -function, which gives the number of integers in the range 1, 2, 3 . . ., N 1, that are relatively prime to N
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