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5 5 sin 2t 1=2
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7=12 < t < 11=12 otherwise
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Fig. 5-10 EXAMPLE 5.8 In Fig. 5-11, R1 10 k
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, R2 50 k
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, Ro 0, and A 105 . Find v2 =v1 . the ampli er is not saturated. Assume
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Fig. 5-11 The sum of currents arriving at node B is zero. Note that vA 0 and vB vd . Therefore, 6
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v1 vd v v vd d 2 0 10 500 50 Since Ro 0, we have v2 Avd 105 vd or vd 10 5 v2
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[CHAP. 5
Substituting vd in (7) into (6), the ratio v2 =v1 is found to be v2 5 5 v1 1 10 5 5 10 5 0:1 10 5
ANALYSIS OF CIRCUITS CONTAINING IDEAL OP AMPS
In an ideal op amp, Ri and A are in nite and Ro is zero. Therefore, the ideal op amp draws zero current at its inverting and noninverting inputs, and if it is not saturated these inputs are at the same voltage. Throughout this chapter we assume op amps are ideal and operate in the linear range unless speci ed otherwise.
EXAMPLE 5.9 The op amp in Fig. 5-12 is ideal and not saturated. Find (a) v2 =v1 ; (b) the input resistance v1 =i1 ; and (c) i1 ; i2 ; p1 (the power delivered by v1 ), and p2 (the power dissipated in the resistors) given v1 0:5 V.
Fig. 5-12 (a) The noninverting terminal A is grounded and so vA 0. Since the op amp is ideal and not saturated, vB 0. Applying KCL at nodes B and C and noting that the op amp draws no current, we get Node B: Node C: Substituting vC in (8) into (9), v2 6:4v1 (b) With VB 0, i1 v1 =5000 and so input resistance v1 =i1 5 k
(c) The input current is i1 v1 =5000. Given that v1 0:5 V, i1 0:5=5000 0:1 mA. To nd i2 , we apply KCL at the output of the op amp; i2 From part (a), v2 3:2 V and vC 1 V. The power delivered by v1 is v2 v vC 2 8000 2000 or v2 =v1 6:4 v1 vC 0 5 10 vC vC vC v2 0 10 1 2 or or vC 2v1 v2 3:2vC (8) (9)
Therefore, i2 1:5 mA.
p1 v1 i1 v2 =5000 50 10 6 W 50 mW 1 Powers in the resistors are
CHAP. 5]
AMPLIFIERS AND OPERATIONAL AMPLIFIER CIRCUITS
: 2 k
: 5 k
: 8 k
: 10 k
p1 k
v2 =1000 0:001 W 1000 mW C p2 k
v2 vC 2 =2000 0:00242 W 2420 mW p5 k
v2 =5000 0:00005 W 50 mW 1 p8 k
v2 =8000 0:00128 W 1280 mW 2 p10 k
v2 =10 000 0:0001 W 100 mW C
The total power dissipated in the resistors is p2 p1 k
p2 k
p5 k
p8 k
p10 k
1000 2420 50 1280 100 4850 mW
INVERTING CIRCUIT
In an inverting circuit, the input signal is connected through R1 to the inverting terminal of the op amp and the output terminal is connected back through a feedback resistor R2 to the inverting terminal. The noninverting terminal of the op amp is grounded (see Fig. 5-13).
Fig. 5-13
To nd the gain v2 =v1 , apply KCL to the currents arriving at node B: v1 v 2 0 R1 R2 and v2 R 2 v1 R1 10 The input resistance of the circuit
The gain is negative and is determined by the choice of resistors only. is R1 .
SUMMING CIRCUIT
The weighted sum of several voltages in a circuit can be obtained by using the circuit of Fig. 5-14. This circuit, called a summing circuit, is an extension of the inverting circuit. To nd the output, apply KCL to the inverting node: v1 v v v 2 n o 0 R1 R2 Rn Rf from which vo   Rf Rf Rf v1 v2 vn R1 R2 Rn 11
EXAMPLE 5.10 Let the circuit of Fig. 5-14 have four input lines with R1 1; R2 1 ; R3 1 ; R4 1, and Rf 1, 2 4 8 all values given in k
. The input lines are set either at 0 or 1 V. Find vo in terms of v4 , v3 , v2 , v1 , given the following sets of inputs: (a) v4 1 V v3 0 v2 0 v1 1 V
AMPLIFIERS AND OPERATIONAL AMPLIFIER CIRCUITS
[CHAP. 5
Fig. 5-14 (b) v4 1 V From (11) vo 8v4 4v3 2v2 v1 Substituting for v1 to v4 we obtain a b vo 9 V vo 14 V v3 1 V v2 1 V v1 0
The set fv4 ; v3 ; v2 ; v1 g forms a binary sequence containing four bits at high (1 V) or low (0 V) values. Input sets given in (a) and (b) correspond to the binary numbers 1001 2 9 10 and 1110 2 14 10 , respectively. With the inputs at 0 V (low) or 1 V (high), the circuit converts the binary number represented by the input set fv4 ; v3 ; v2 ; v1 g to a negative voltage which, when measured in V, is equal to the base 10 representation of the input set. The circuit is a digital-to-analog converter.
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