display barcode in ssrs report Fig. 9-17 (a) Since VZ is the voltage at node a, (9.5) gives vo R2 V R1 Z in Software

Drawing Code 39 Full ASCII in Software Fig. 9-17 (a) Since VZ is the voltage at node a, (9.5) gives vo R2 V R1 Z

Fig. 9-17 (a) Since VZ is the voltage at node a, (9.5) gives vo R2 V R1 Z
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So long as iZ ! 0:1IZ , a regulated value of vo can be achieved by adjustment of R2 . (b) Regulation is preserved and the diode current iZ iS i1 does not exceed its rated value IZ if 0:1IZ iS i1 IZ or 0:1IZ VS VZ VZ RS R1 IZ
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  R 0:1IZ RS 1 S VZ R1
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  R IZ R S 1 S V Z R1
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The circuit of Fig. 9-18(a) is a limiter; it reduces the signal gain to some limiting level rather than imposing the abrupt clamping action of the circuit of Problem 9.8. (a) Determine the limiting value V of vo at which the diode D becomes forward-biased, thus establishing a second feedback
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+V i4 R4 R3 _
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Slope = _
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R2 R1 _V R1 l R 2
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D + R2 i2
Vl R3 R2 Slope = _ R2 + R3 R1 (b)
Fig. 9-18
path through R3 . Assume an ideal op amp and a diode characterized by Fig. 2-2(a). (b) Determine the relationship between vo and vS , and sketch the transfer characteristic.
(a) The diode voltage vD is found by writing a loop equation. Since the inverting input is a virtual ground, vo appears across R2 and vD vo i3 R3 vo When vD 0; vo V , and (1) gives V R3 V R4 2 V vo R R3 R4 3 1
(b) For vo > V , the diode blocks and R2 constitutes the only feedback path. Since i1 i2 , vS v o R1 R2 3
For vo V , the diode conducts and the parallel combination of R2 and R3 forms the feedback path. Since now i1 i2 i3 i4 ,   vS v v V o o 4 R1 R2 R3 R4 It follows from (2), (3), and (4) that 8 > R2 v > < R S 1 vo R2 R2 R3 > > R3 : v V R2 R3 R1 S R2 R3 R4 This transfer characteristic is plotted in Fig. 9-18(b).
for vS <
R1 R3 V R2 R4 R R for vS ! 1 3 V R2 R4
What modi cations and speci cations will change the circuit of Fig. 9-16(a) into a 3-V squarewave generator, if vS 0:02 sin !t V Sketch the circuit transfer characteristic and the input and output waveforms.
OPERATIONAL AMPLIFIERS
[CHAP. 9
Modify the circuit by removing R2 , and specify Zener diodes such that VZ1 VZ2 3 V. The transfer characteristic of Fig. 9-16(b) will change to that of Fig. 9-19(a). The time relationship between vS and vo will be that displayed in Fig. 9-19(b).
Lo, V
L, V
L S, V
Fig. 9-19
Design a rst-order low-pass lter with dc gain of magnitude 2 and input impedance 5 k. The gain should be at to 100 Hz.
The lter is shown in Fig. 9-8. For an ideal op amp, Problem 9.4 gives Z1 R1 5 k. The dc gain is given by (9.20) as A 0 R=R1 , whence R 2R1 10 k. Figure 9-8(b) shows that the magnitude of the gain is at to ! 0:1=RC, so the capacitor must be sized such that C 0:1 0:1 15:9 nF 2fR 2 100 10 103
The analog computer utilizes operational ampli ers to solve di erential equations. Devise an analog solution for i t ; t > 0, in the circuit of Fig. 9-20(a). Assume that you have available an inverting integrator with unity gain R1 C1 1 , inverting ampli ers, a variable dc source, and a switch.
For t > 0, the governing di erential equation for the circuit of Fig. 9-20(a) may be written as di V R b i dt L L 1
The sum on the right side of (1) can be simulated by the left-hand inverting adder of Fig. 9-20(b), where vo1 di=dt and where R2 and R3 are chosen such that R3 =R2 R=L. Then vo2 vo1 dt will be an analog of i t , on a scale of 1 A/V.
Find the relationship between vo and vi in the circuit of Fig. 9-21.
Since the inverting terminal is a virtual ground, the Laplace-domain input current is given by Ii Vi V sRC 1 i 2 R Rk1=sC sR C 2R
With zero current owing into the op amp inverting terminal, current division yields I2 I1 1=sC 1 Vi sRC 1 Vi I R 1=sC i sRC 1 R sRC 2 R sRC 2
CHAP. 9]
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