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BUCK-BOOST CONVERTER
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The SMPS circuit of Fig. 10-6 is a buck-boost converter. The value of output voltage for this converter may either be less than or greater than the input voltage, depending on the value of duty cycle D. Unlike the buck and boost converters, the buck-boost converter produces an output voltage with polarity opposite to input voltage V1 . The polarity of v2 and the direction of I2 in Fig. 10-6 are chosen so that V2 hv2 i ! 0 and I2 ! 0.
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Fig. 10-6
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Buck-boost converter
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CHAP. 10]
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For a large value of capacitor C, reasonable approximations are that the time-varying component of iD ows through C and that the voltage across RL is constant. For periodic switching of Q, voltage vL and current iC are periodic after initial transients subside. As a direct consequence of the preceding approximations, vL and iL can be appropriately determined by (10.1) and (10.2) when Q is ON (let VC 0 and by (1) and (2) of Example 10.1 when Q is OFF. Since load current I2 is the average value of iD , iC iD I2 . Figure 10-7 shows sketches of the resulting waveforms for vL ; iL ; iC ; and iD .
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Fig. 10-7 Buck-boost converter waveforms
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Based on (10.3) and the vL waveform of Fig. 10-7, V1 DTs V2 1 D Ts Rearrangement gives the ideal buck-boost converter voltage gain as GV V2 D V1 1 D 10:9
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As with the boost converter, the buck-boost converter gain is not a linear function of duty cycle D. Further, (10.9) shows that the ideal gain GV approaches in nity as D approaches 1. When parasitic 0 resistances of the inductor and capacitor are considered, the actual gain GV departs signi cantly from the ideal gain for values of D > 0:75. (See Problem 10.14.) The common case of continuous current iL exists only if the value of L ! Lc (critical inductance) that results in marginally continuous conduction for iL . For such case, Imin 0 in Fig. 10-7 and iL 0 0. By application of (10.2), iL t V1 t Lc 0 t DTs
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[CHAP. 10
Evaluate for t DTs and use (10.9) to yield Imax iL DTs For the triangular waveform of iD , I2 hiD i 1 1 D Ts V I 2 1 D 2 Ts 2 max Ts 2Lc V1 V 1 D DTs 2 Ts Lc Lc
But I2 V2 =RL which can be equated to the above expression for I2 . After rearrangement, Lc 1 D 2 Ts RL 1 D 2 RL 2 2fs 10:10
Example 10.4. A buck-boost converter with a 30-kHz switching frequency is operating with D 0:25. connected load is described by RL 10 . Find the value of critical inductance so that iL is continuous. By (10.10),
Lc
1 D 2 RL 1 0:25 2 10 93:75 H 2fs 2 30 103
SPICE ANALYSIS OF SMPS
For simulation of near ideal (lossless) SMPS, the switch element Q can readily be modeled using the PSpice voltage-controlled switch. The element speci cation statement for the voltage-controlled switch has the form S n1 n2 c1 c2 VCS Any alpha-numeric combination su x can follow S to uniquely specify the voltage-controlled switch. The nodes are clari ed by Fig. 10-8. A fast rise and fall time (5 ns), 1-V pulse should be used for the control voltage vSW . Accepting the default ON state and OFF state control voltages of 1 V and 0 V, respectively, results in duty cycle ON time approximately equal to the pulse duration. For minimum
Fig. 10-8 Voltage-controlled switch
CHAP. 10]
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conduction losses, the ON state resistance of the voltage-controlled switch should be speci ed in the .MODEL statement by .MODEL VCS VSWITCH (RON=1e-6)
Example 10.5. Use SPICE methods to model the buck converter of Fig. 10-2; let D 0:5, fs 25 kHz, L 100 H, C 50 F, and RL 5 . Generate the set of waveforms analogous to Fig. 10-3. The netlist code follows, where the initial conditions on inductor current and capacitor voltage were determined after running a large integer number of cycles to nd the repetitive values.
Ex10_5.CIR * BUCK CONVERTER * D=DUTY CYCLE, fs=SWITCHING FREQUENCY .PARAM D=0.5 fs=25e3Hz V1 1 0 DC 12V SW 1 2 4 2 VCS VSW 4 2 PULSE(0V 1V 0s 5ns 5ns {D/fs} {1/fs}) L 2 3 100uH IC=0.6A D 0 2 DMOD C 3 0 50uF IC=6V RL 3 0 5ohm .MODEL DMOD D(N=0.01) .MODEL VCS VSWITCH (RON=1e-6ohm) .TRAN 5us 0.2ms 0s 100ns UIC .PROBE .END
Execute hEx10_5.CIRi and use the Probe feature of PSpice to plot the waveforms of Fig. 10-9.
Fig. 10-9
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