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CLIPPING AND CLAMPING OPERATIONS
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Diode clipping circuits separate an input signal at a particular dc level and pass to the output, without distortion, the desired upper or lower portion of the original waveform. They are used to eliminate amplitude noise or to fabricate new waveforms from an existing signal.
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Example 2.15. Figure 2-17(a) shows a positive clipping circuit, which removes any portion of the input signal vi that is greater than Vb and passes as the output signal vo any portion of vi that is less than Vb . As you can see, vD is negative when vi < Vb , causing the ideal diode to act as an open circuit. With no path for current to ow through R, the value of vi appears at the output terminals as vo . However, when vi ! Vb , the diode conducts, acting as a short circuit and forcing vo Vb . Figure 2-17(b), the transfer graph or transfer characteristic for the circuit, shows the relationship between the input voltage, here taken as vi 2Vb sin !t, and the output voltage.
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Clamping is a process of setting the positive or negative peaks of an input ac waveform to a speci c dc level, regardless of any variation in those peaks.
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Example 2.16. An ideal clamping circuit is shown in Fig. 2-18(b), and a triangular ac input waveform in Fig. 2-18(a). If the capacitor C is initially uncharged and Vb 0, the ideal diode D is forward-biased for 0 < t T=4, and it acts as a short circuit while the capacitor charges to vC Vp . At t T=4, D open-circuits, breaking the only possible discharge path for the capacitor. Thus, the value vC Vp is preserved; since vi can never exceed Vp , D remains reverse-biased for all t > T=4, giving vo vD vi Vp . The function vo is sketched in Fig. 2-18(c); all positive peaks are clamped at zero, and the average value is shifted from 0 to Vp . Example 2.17. For the clamping circuit of Fig. 2-18(b), let vi 10 sin 2000t V, VB 5 V, and C 10 F. Assume an ideal diode and use SPICE methods to determine output voltage vo . The netlist code describing the circuit is shown below. Since the capacitor will charge so that vC VB 5 V, this value is set as an initial condition (IC 5 V to circumvent the transient response.
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_ (a) _
_ 2V
_ 2V
t (b)
Fig. 2-17
Li Lo
1 Vp +
C +L _
T/2 3T/4
5T/4
T/4 T/2 3T/4 T
D 3 + _VB 0
_ 2V
Fig. 2-18
Ex2_17.CIR - Clamping circuit vi 1 0 SIN ( 0V 10V 1kHz ) C 1 2 10uF IC=5V ; Set initial condition D 2 3 DMOD VB 3 0 5V .MODEL DMOD D(n=0.0001) ; Ideal diode .TRAN 1us 2ms UIC .PROBE .END
Execute <Ex2_17.CIR> and use the Probe feature of PSpice to plot the resulting output voltage vo V 2 as shown by Fig. 2-19(a) where it is seen that the output voltage is simply vi clamped so that the maximum value is equal to VB 5 V.
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Fig. 2-19
Example 2.18. The positive clamping circuit of Fig. 2-18(b) can be changed to a negative clamping circuit by inverting battery VB . Make this change VB 5 V) and use SPICE methods to determine the output voltage vo for the circuit if vi and C have the values of Example 2.17. The netlist code of Example 2.17 can be modi ed to describe the reversal of VB by simply assigning a value of 5 V ( VB 3 0 5V) or by reversing the order of the node listing ( VB 0 3 5V). Since the capacitor will charge so that vC 15 V, set IC 15 V to yield an immediate steady-state solution. Execution of the modi ed netlist code (available at the author website as <Ex2_18.CIR>) and use of the Probe feature of PSpice leads to the plot of Fig. 2-19(b) where it is seen that the output voltage vo V 2 is vi clamped to the maximum value of VB 5 V.
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