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iD1 evD1 =VT 1
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10 10 3 91 nA e0:3=0:02587 1
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For the circuit of Fig. 2-22(a), sketch the waveforms of vL and vD if the source voltage vS is as given in Fig. 2-22(b). The diode is ideal, and RL 100 .
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SEMICONDUCTOR DIODES
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RS = 10 W +
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_ (a)
LL and LD, V
t, ms
Fig. 2-22
If vS ! 0, D conducts, so that vD 0 and vL RL 100 v 0:909vS v RL RS S 100 10 S Sketches of vD and vL are shown in Fig. 2-22(c).
If vS < 0, D blocks, so that vD vS and vL 0.
Extend the ideal diode analysis procedure of Section 2.2 to the case of multiple diodes by solving for the current iL in the circuit of Fig. 2-23(a). Assume D1 and D2 are ideal. R2 RL 100 , and vS is a 10-V square wave of period 1 ms.
iD2 D2 D1
iD2 D2 D1
D1 +
iL RL
iL RL
iL RL
_ (a) (b) (c)
Fig. 2-23
SEMICONDUCTOR DIODES
[CHAP. 2
Assume both diodes are forward-biased, and replace each with a short circuit as shown in Fig. 2-23(b). Step 2: Since D1 is on, or in the zero-impedance state, current division requires that Step 1: iD2 Hence, by Ohm s law, iL iD1 Step 3: vS RL 2 0 i 0 R2 0 L 1
Observe that when vS 10 > 0, we have, by (2), iD1 10=100 0:1 A > 0. Also, by (1), iD2 0. Thus all diode currents are greater than or equal to zero, and the analysis is valid. However, when vS 10 < 0, we have, by (2), iD1 10=100 0:1 A < 0, and the analysis is no longer valid. Step 4: Replace D1 with an open circuit as illustrated in Fig. 2-23(c). Now obviously iD1 0 and, by Ohm s law, iL iD2 Further, voltage division requires that vD1 R2 v R2 RL S vS 10 0:05 A R2 RL 100 100
so that vD1 < 0 if vS < 0, verifying that D1 is actually reverse-biased. Note that if D2 had been replaced with an open circuit, we would have found that vD2 vS 10 V > 0, so D2 would not actually have been reverse-biased.
In the circuit of Fig. 2-24, D1 and D2 are ideal diodes.
D1 _
Find iD1 and iD2 .
D2 + _
iD1 +
500 W iS + _ VS = 5 V b
+ V1 = 5 V _
+ _ V2 = 3 V
Fig. 2-24 Because of the polarities of D1 and D2 , it is necessary that iS ! 0. Thus, vab VS V1 . But vD1 vab V1 ; therefore, vD 0 and so iD1  0, regardless of conditions in the right-hand loop. It follows that iD2 iS . Now using the analysis procedure of Section 2.2, we assume D2 is forward-biased and replace it with a short circuit. By KVL, iD2 VS V2 5 3 4 mA 500 500
Since iD2 ! 0, D2 is in fact forward-biased and the analysis is valid.
The logic OR gate can be utilized to fabricate composite waveforms. Sketch the output vo of the gate of Fig. 2-25(a) if the three signals of Fig. 2-25(b) are impressed on the input terminals. Assume that diodes are ideal.
For this circuit, KVL gives v1 v2 vD1 vD2 v1 v3 vD1 vD3
CHAP. 2]
SEMICONDUCTOR DIODES
D1 + D2 +
L1 L2 L3
D3 + +
0 1 2 3 4 5 6
_ _ _ _
t (c)
Fig. 2-25 i.e., the diode voltages have the same ordering as the input voltages. Suppose that v1 is positive and exceeds v2 and v3 . Then D1 must be forward-biased, with vD1 0 and, consequently, vD2 < 0 and vD3 < 0. Hence, D2 and D3 block, while v1 is passed as vo . This is so in general: The logic of the OR gate is that the largest positive input signal is passed as vo , while the remainder of the input signals are blocked. If all input signals are negative, vo 0. Application of this logic gives the sketch of vo in Fig. 2-25(c).
The diode in the circuit of Fig. 2-26(a) has the nonlinear terminal characteristic of Fig. 2-26(b). Find iD and vD analytically, given vS 0:1 cos !t V and Vb 2 V.
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