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Fig. 2-26
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SEMICONDUCTOR DIODES
[CHAP. 2
The Thevenin equivalent circuit for the network to the left of terminals a; b in Fig. 2-26(a) has VTh RTh 100 2 0:1 cos !t 1 0:05 cos !t 200 100 2 50  200 0:7 0:5 50  0:004 Now by V
The diode can be modeled as in Fig. 2-11(b), with VF 0:5 V and RF
Together, the Thevenin equivalent circuit and the diode model form the circuit in Fig. 2-26(c). Ohm s law, VTh VF 1 0:05 cos !t 0:5 5 0:5 cos !t mA RTh RF 50 50 vD VF RF iD 0:5 50 0:005 0:0005 cos !t 0:75 0:025 cos !t iD
Solve Problem 2.7 graphically for iD .
The Thevenin equivalent circuit has already been determined in Problem 2.7. By (2.4), the dc load line is given by iD VTh v 1 v D D 20 20vD RTh RTh 50 50 mA 1
In Fig. 2-27, (1) has been superimposed on the diode characteristic, replotted from Fig. 2-26(b). As in Example 2.7, equivalent time scales for vTh and iD are laid out adjacent to the characteristic curve. Since the diode characteristic is linear about the Q point over the range of operation, only dynamic load lines corresponding to the maximum and minimum of vTh need be drawn. Once these two dynamic load lines are constructed parallel to the dc load line, iD can be sketched.
Use the small-signal technique of Section 2.6 to nd iD and vD in Problem 2.7.
The Thevenin equivalent circuit of Problem 2.7 is valid here. Moreover, the intersection of the dc load line and the diode characteristic in Fig. 2-27 gives IDQ 5 mA and VDQ 0:75 V. The dynamic resistance is, then, by (2.5), rd vD 0:7 0:5 50  0:004 iD
We now have all the values needed for analysis using the small-signal circuit of Fig. 2-12. By Ohm s law, vth 0:05 cos !t 0:5 cos !t mA 50 50 RTh rd vd rd id 50 0:0005 cos !t 0:025 cos !t V iD IDQ id 5 0:5 cos !t mA vD VDQ vd 0:75 0:025 cos !t V id
A voltage source, vS 0:4 0:2 sin !t V, is placed directly across a diode characterized by Fig. 2-26(b). The source has no internal impedance and is of proper polarity to forward-bias the diode. (a) Sketch the resulting diode current iD . (b) Determine the value of the quiescent current IDQ .
(a) A scaled plot of vS has been laid out adjacent to the vD axis of the diode characteristic in Fig. 2-28. With zero resistance between the ideal voltage source and the diode, the dc load line has in nite slope and vD vS . Thus, iD is found by a point-by-point projection of vS onto the diode characteristic,
iD, mA VTh /RTh
DC load line
Dynamic load lines
iD, mA
5.0 4
IDQ = 5 mA
Q VTh
0.95 1.0 1.05
LD, V
LTh, V
Fig. 2-27
iD, mA
LD, V
t1 t2 t3
Fig. 2-28
SEMICONDUCTOR DIODES
[CHAP. 2
followed by re ection through the iD axis. Notice that iD is extremely distorted, bearing little resemblance to vS . (b) Quiescent conditions obtain when the ac signal is zero. In this case, when vS 0:4 V, iD IDQ 0.
In the circuit of Fig. 2-3(a), assume RS R1 200 , RL 50 k, and vS 400 sin !t V. The diode is ideal, with reverse saturation current Io 2 A and a peak inverse voltage (PIV) rating of VR 100 V. (a) Will the diode fail in avalanche breakdown (b) If the diode will fail, is there a value of RL for which failure will not occur
(a) From Example 2.1, vTh RTh R1 200 v 400 sin !t 200 sin !t R1 RS S 200 200 R1 RS 200 200 100  R1 RS 200 200 V
The circuit to be analyzed is that of Fig. 2-3(c); the instants of concern are when !t 2n 1 =2 for n 1; 2; 3; . . . ; at which times vTh 200 V and thus vD is at its most negative value. An application of KVL yields vD vTh iD RTh RL 200 2 10 6 100 50 103 199:9 V Since vD < VR 100 V, avalanche failure occurs. (b) From (1), it is apparent that vD ! 100 V if RL ! vTh vD 200 100 RTh 100 50 M iD 2 10 6 1
In the circuit of Fig. 2-29, vS is a 10-V square wave of period 4 ms, R 100 , and C 20 F. Sketch vC for the rst two cycles of vS if the capacitor is initially uncharged and the diode is ideal.
D iD + C _
Fig. 2-29 In the interval 0 t < 2 ms, vC t vS 1 e t=RC 10 1 e 500t For 2 t < 4 ms, D blocks and the capacitor voltage remains at vC 2 ms 10 1 e 500 0:002 6:32 V For 4 t < 6 ms, vC t vS vS 6:32 e t 0:004 =RC 10 10 6:32 e 500 t 0:004 And for 6 t < 8 ms, D again blocks and the capacitor voltage remains at vC 6 ms 10 10 6:32 e 500 0:002 8:654 V V V
CHAP. 2]
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