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Print Code 39 Extended in Software (d) With ICEO 0, (3.2) yields

(d) With ICEO 0, (3.2) yields
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In the pnp Si transistor circuit of Fig. 3-13, RB 500 k, RC 2 k, RE 0, VCC 15 V, ICBO 20 A, and 70. Find the Q-point collector current ICQ .
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By (3.3), ICEO 1 ICBO 70 1 20 10 6 1:42 mA. Now, application of the KVL around the loop that includes VCC , RB , RE 0 , and ground VCC VBEQ IBQ RB Thus, by (3.2), ICQ IBQ ICEO 70 28:6 10 6 1:42 10 3 3:42 mA so that IBQ VCC VBEQ 15 0:7 28:6 A RB 500 103
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The Si transistor of Fig. 3-14 is biased for constant base current. If 80, VCEQ 8 V, RC 3 k, and VCC 15 V, nd (a) ICQ and (b) the required value of RB . (c) Find RB if the transistor is a Ge device.
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CHARACTERISTICS OF BIPOLAR JUNCTION TRANSISTORS
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[CHAP. 3
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RC + RB RC iC RB _ iB B RE E iE C iC + _ VCC
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Fig. 3-13
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Fig. 3-14
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(a) By KVL around the collector-emitter circuit, ICQ VCC VCEQ 15 8 2:333 mA Rc 3 103 ICQ 2:333 10 3 29:16 A 80
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(b) If leakage current is neglected, (3.2) gives IBQ
Since the transistor is a Si device, VBEQ 0:7 V and, by KVL around the outer loop, RB (c) VCC VBEQ 15 0:7 490:4 k IBQ 29:16 10 6
The only di erence here is that VBEQ 0:3 V; thus RB 15 0:3 504:1 k 29:16 10 6
The Si transistor of Fig. 3-15 has 0:99 and ICEO 0. Also, VEE 4 V and VCC 12 V. (a) If IEQ 1:1 mA, nd RE . (b) If VCEQ 7 V, nd RC .
iE E C iC
RE B + VEE _ iB
_ + VCC
Fig. 3-15 (a) By KVL around the emitter-base loop, VEE VBEQ 4 0:7 3 IEQ 1:1 10 3
RE
CHAP. 3]
CHARACTERISTICS OF BIPOLAR JUNCTION TRANSISTORS
(b) By KVL around the transistor terminals (which constitute a closed path), VCBQ VCEQ VBEQ 7 0:7 6:3 V With negligible leakage current, (3.1) gives ICQ IEQ 0:99 1:1 10 3 1:089 mA Finally, by KVL around the base-collector loop, RC VCC VCBQ 12 6:3 5:234 k ICQ 1:089 10 3
Collector characteristics for the Ge transistor of Fig. 3-15 are given in Fig. 3-16. If VEE 2 V, VCC 12 V, and RC 2 k, size RE so that VCEQ 6:4 V.
iC, mA
iE = 7 mA 6 mA 5 mA 4 mA Q 3 mA 2 mA
, iC for hf b
,LCB for hob
, iC for hob
, iE for hf b
1 mA 0
_ 10
_ 12
_ 14
_ 16
_ 18
_ 20
LCB , V
Fig. 3-16 We construct, on Fig. 3-16, a dc load line having vCB intercept VCC 12 V and iC intercept VCC =RC 6 mA. The abscissa of the Q point is given by KVL around the transistor terminals: VCBQ VCEQ VBEQ 6:4 0:3 6:1 V With the Q point de ned, we read IEQ 3 mA from the graph. leads to RE Now KVL around the emitter-base loop
VEE VBEQ 2 0:3 566:7  IEQ 3 10 3
The circuit of Fig. 3-17 uses current- (or shunt-) feedback bias. The Si transistor has ICEO % 0, VCEsat % 0, and hFE 100. If RC 2 k and VCC 12 V, size RF for ideal maximum symmetrical swing (that is, location of the quiescent point such that VCEQ VCC =2 .
CHARACTERISTICS OF BIPOLAR JUNCTION TRANSISTORS
[CHAP. 3
+VCC RC CC
RF iS 2 CC 3 iB
4 iC
6 + iL
_ Ri 0 Ro
Fig. 3-17
Application of KVL to the collector-emitter bias circuit gives IBQ ICQ RC VCC VCEQ With ICQ hFE IBQ , this leads to IBQ VCC VCEQ 12 6 29:7 A hFE 1 RC 100 1 2 103 VCEQ VBEQ 6 0:7 178:5 k IBQ 29:7 10 6
Then, by KVL around the transistor terminals, RF
For the ampli er of Fig. 3-17, CC 100 F, RF 180 k, RL 2 k, RS 100 k, VCC 12 V, and vS 4 sin 20 103 t V. The transistor is described by the default npn model of Example 3.2. Use SPICE methods to (a) determine the quiescent values (IBQ ; ICQ ; VBEQ ; VCEQ ) and (b) plot the input and output currents and voltages vS ; iS ; vL ; iL .
(a) The netlist code that follows models the circuit:
Prb3_14.CIR - CE amplifier vS 1 0 SIN(0V 4V 10kHz) RS 1 2 100kohm CC1 2 3 100uF Q 4 3 0 QNPN RF 3 4 180kohm RC 4 5 2kohm VCC 5 0 12V CC2 4 6 100uF RL 6 0 2kohm .MODEL QNPN NPN() ; Default transistor .DC VCC 12V 12V 1V .PRINT DC IB(Q) IC(Q) V(3) V(4) .TRAN 1us 0.1ms ; Signal values .PROBE .END
Execute hPrb3_14.CIRi and poll the output le to nd IBQ IB Q 29:3 A, ICQ IC Q 2:93 mA, VBEQ V 3 0:80 V, and VCEQ V 4 6:08 V. Since VCEQ VCC =2, the transistor is biased for maximum symmetrical swing.
CHAP. 3]
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