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1 1 1 0:454 mS Rdc RC RE 2:2 103
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From (3.14), the ac load line intersects the vCE axis at vCE max VCEQ ICQ Rac 8:01 3:177 10 3 1 103 11:187 V
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CHAP. 3]
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CHARACTERISTICS OF BIPOLAR JUNCTION TRANSISTORS
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Since vCE max < 2VCEQ , cuto occurs before saturation and thus sets Vcem . With the large capacitors appearing as ac shorts, v v iL L ce RL RL or, in terms of peak values, ILm Vcem vCE max VCEQ 11:187 8:01 1:588 mA RL RL 2 103
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In the circuit of Fig. 3-8(a), RC 300 ; RE 200 ; R1 2 k; R2 15 k; VCC 15 V, and 110 for the Si transistor. Assume that ICQ % IEQ and VCEsat % 0. Find the maximum symmetrical swing in collector current (a) if an ac base current is injected, and (b) if VCC is changed to 10 V but all else remains the same.
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(a) From (3.5) and (3.7), RB so ICQ 2 103 15 103 2 103 1:765 k and VBB 15 1:765 V 3 17 103 17 10 VBB VBEQ 1:765 0:7 4:93 mA % IEQ RB = 1 RE 1765=111 200
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By KVL around the collector-emitter circuit with ICQ % IEQ , VCEQ VCC ICQ RC RE 15 4:93 10 3 200 300 12:535 V Since VCEQ > VCC =2 7:5 V, cuto occurs before saturation, and iC can swing 4:93 mA about ICQ and remain in the active region. b VBB so that and ICQ % IEQ R1 2 103 VCC 10 1:1765 V R1 R2 17 103
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VBB VBEQ 1:1765 0:7 2:206 mA RB = 1 RE 1765=111 200
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VCEQ VCC ICQ RC RE 10 2:206 10 3 0:5 8:79 V
Since VCEQ > VCC =2 5 V, cuto again occurs before saturation, and iC can swing 2:206 mA about ICQ and remain in the active region of operation. Here, the 33.3 percent reduction in power supply voltage has resulted in a reduction of over 50 percent in symmetrical collector-current swing.
If a Si transistor were removed from the circuit of Fig. 3-8(a) and a Ge transistor of identical were substituted, would the Q point move in the direction of saturation or of cuto
Since R1 ; R2 , and VCC are unchanged, RB and VBB would remain unchanged. However, owing to the di erent emitter-to-base forward drops for Si (0.7 V) and Ge (0.3 V) transistors, ICQ % VBB VBEQ RB = 1 RE
would be higher for the Ge transistor. Thus, the Q point would move in the direction of saturation.
In the circuit of Fig. 3-10(a), VCC 12 V; RC RL 1 k; RE 100 , and CC CE ! 1. The Si transistor has negligible leakage current, and 100. If VCEsat 0 and the transistor is to have -independent bias (by having R1 kR2 RE =10 , size R1 and R2 for maximum symmetrical swing.
Evaluating Rac and Rdc , we nd Rac RL kRC 1 103 1 103 500  1 103 1 103 Rdc RC RE 1 103 100 1100 
CHARACTERISTICS OF BIPOLAR JUNCTION TRANSISTORS
[CHAP. 3
Thus, according to (3) of Problem 3.25, maximum symmetrical swing requires that ICQ Now, VCC 12 7:5 mA Rac Rdc 500 1100 RE 100 100 RB R1 kR2 1 k 10 10
and, by (3.6) and (2) of Problem 3.17, !   RB 1 1 103 100 1 VBB RE ICQ VBEQ 100 7:5 10 3 0:7 1:53 V 100 100 Finally, from (3.5), R1 RB 1 103 1:34 k 1 VBB =VCC 1 1:53=12 and R2 RB VCC 1 103 12 10:53 k 1:53 VBB
The Si transistor of Fig. 3-10(a) has VCEsat ICBO 0 and 75. CE is removed from the circuit, and CC ! 1. Also, R1 1 k; R2 9 k; RE RL RC 1 k, and VCC 15 V. (a) Sketch the dc and ac load lines for this ampli er on a set of iC -vCE axes. (b) Find the maximum undistorted value of iL , and determine whether cuto or saturation limits iL swing.
a Rdc RC RE 1 103 1 103 2 k and By (3.5), VBB R1 1 103 VCC 15 1:667 V R2 9 103 and RB R1 kR2 1 103 9 103 900  1 103 9 103 Rac RE RC kRL 1 103 1 103 1 103 1:5 k 1 103 1 103
and from (3.7), ICQ 1 VBB VBEQ 75 1 1:667 0:7 0:96 mA RB 1 RE 900 75 1 1 103
By KVL around the collector loop and (2) of Problem 3.17,     1 75 1 RE ICQ 15 1 103 1 103 0:96 10 3 13:07 V VCEQ VCC RC 75 The ac load-line intercepts now follow directly from (3.13) and (3.14): iC max VCEQ 13:07 ICQ 0:96 10 3 9:67 mA Rac 1:5 103
vCE max VCEQ ICQ Rac 13:07 0:96 10 3 1:5 103 14:51 V The dc load-line intercepts follow from (3.9): VCC 15 7:5 mA Rdc 2 103 vCE -axis intercept VCC 15 V iC -axis intercept The required load lines are sketched in Fig. 3.25. (b) Since ICQ < 1 iC max , it is apparent that cuto limits the undistorted swing of ic to ICQ 1:92 mA. 2 By current division, iL RE 1 103 i 0:96 mA 0:48 mA RE RL c 1 103 1 103
CHAP. 3]
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