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By a method called self-bias, the Q point of a JFET ampli er may be established using only a single resistor from gate to ground [Fig. 4-5(b) with VGG 0 : If RD 3 k; RS 2 k, RG 5 M, and VDD 20 V in Fig. 4-5(b), and the JFET characteristics are given by Fig. 4-6, nd (a) IDQ ; b VGSQ , and (c) VDSQ .
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(a) On Fig. 4-6(a) we construct a transfer bias line having a vGS intercept of VGG 0 and a slope of 1=RS 0:5 mS; the ordinate of its intersection with the transfer characteristic is IDQ 1:15 mA. (b) The abscissa of the Q point of Fig. 4-6(a) is VGSQ 2:3 V. (c) The dc load line from Example 4.2, already constructed on Fig. 4-6(b), is applicable here. The Q point was established at IDQ 1:15 mA in (a); the corresponding abscissa is VDSQ % 14:2 V.
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Work Problem 4.3, except with the JFET described by the parameter values of Example 4.1, using SPICE methods to illustrate the ease with which quiescent values for a JFET circuit can be determined.
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The netlist code below describes the circuit of Fig. 4-5(b) with VGG 0.
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Prb4_4.CIR - Self-bias RG 1 0 5MEGohm ; VGG not used RS 2 0 2kohm RD 3 4 3kohm VDD 4 0 20V J 3 1 2 NJFET .MODEL NJFET NJF( Vto=-4V Beta=0.0005ApVsq + Rd=1ohm Rs=1ohm CGS=2pF CGD=2pF) .DC VDD 20V 20V 1V .PRINT DC ID(J) V(1,2) V(3,2) .END
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Execute <Prb4_4.CIR> and examine the output le (b) VGSQ V 1; 2 2:44 V, and (c) VDSQ V 3; 2 13:9 V.
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(a) IDQ ID J 1:22 mA,
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Replace the JFET of Fig. 4-5 with an n-channel enhancement-mode MOSFET characterized by Fig. 4-8. Let VDD 16 V, VGSQ 8 V; VDSQ 12 V; IDQ 1 mA; R1 5 M, and R2 3 M. Find (a) VGG ; b RS , and (c) RD .
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(a) By (4.3), VGG R1 VDD = R1 R2 10 V: (b) Application of KVL around the smaller gate-source loop of Fig. 4-5(b) with iG 0 leads to RS (c) VGG VGSQ 10 8 2 k IDQ 1 10 3
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Using KVL around the drain-source loop of Fig. 4-5(b) and solving for RD yield RD VDD VDSQ IDQ RS 16 12 1 10 3 2 103 2 k IDQ 1 10 3
The JFET ampli er of Fig. 4-15 shows a means of self-bias that allows extremely high input impedance even if low values of gate-source bias voltage are required. Find the Thevenin equivalent voltage and resistance for the network to the left of a; b.
CHAP. 4]
CHARACTERISTICS OF FIELD-EFFECT TRANSISTORS AND TRIODES
+ VDD
R2 ii CC a G
R3 _ R1 RS
_ Zin b Zo
Fig. 4-15
With a; b open there is no voltage drop across R3 , and the voltage at the open-circuited terminals is determined by the R1 -R2 voltage divider: vTh VGG R1 V R1 R2 DD
With VDD deactivated (shorted), the resistance to the left of a; b is RTh RG R3 R1 R2 R1 R2
It is apparent that if R3 is made large, then RG Zin is large regardless of the values of R1 and R2 .
The manufacturer s speci cation sheet for a certain kind of n-channel JFET has nominal and worst-case shorted-gate parameters as follows:
Value maximum nominal minimum IDSS ; mA 7 6 5 Vp0 ; V 4.2 3.6 3.0
Sketch the nominal and worst-case transfer characteristics that can be expected from a large sample of the device.
Values can be calculated for the nominal, maximum, and minimum transfer characteristics using (4.2) over the range Vp0 vGS 0. The results are plotted in Fig. 4-16.
A self-biased JFET ampli er (Fig. 4-15) is to be designed with VDSQ 15 V and VDD 24 V, using a device as described in Problem 4.7. For the control of gain variation, the quiescent drain current must satisfy IDQ 2 0:4 mA regardless of the particular parameters of the JFET utilized. Determine appropriate values of RS and RD .
Quiescent points are rst established on the transfer characteristics of Fig. 4-16: Qmax at IDQ 2:4 mA, Qnom at IDQ 2:0 mA, and Qmin at IDQ 1:6 mA. A transfer bias line is then constructed to pass through the origin (i.e., we choose VGG 0) and Qnom . Since its slope is 1=RS , the source resistor value may be determined as
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