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depletion-mode operation VGSQ < 0 and (b) enhancement-mode operation VGSQ > 0 . available from author website.) Ans: a R1 > 2:71 k; b R1 < 2:71 k 4.45
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The common-gate JFET ampli er of Problem 4.23 is not biased for maximum symmetrical swing. Shift the bias point by letting R1 10 k and R2 5 k while all else is unchanged. Does the ampli er bias point move closer to the condition of maximum symmetrical swing Ans: Yes; VDSQ 6:59 V In the circuit of Fig. 4-33, RG ) RS1 ; RS2 . The JFET is described by (4.2), IDSS 10 mA; Vp0 4 V, VDD 15 V; VDSQ 10 V, and VGSQ 2 V. Find (a) RS1 ; b RS2 , and (c) vS : Ans: a 800 ; b 1:2 k; c 5 V
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Transistor Bias Considerations
INTRODUCTION
In the initial design of transistor circuits, the quiescent operating point is carefully established to ensure that the transistor will operate within speci ed limits. Completion of the design requires a check of quiescent-point variations due to temperature changes and unit-to-unit parameter di erences, to ensure that such variations are within an acceptable range. As the principles of operation of the BJT and FET di er greatly, so do the associated methods of Q-point stabilization.
b UNCERTAINTY AND TEMPERATURE EFFECTS IN THE BJT
Uncertainty as to the value of may be due either to unit-to-unit variation (which may reach 200 percent or more) or to temperature variation (1 percent/8C or less); however, since unit-to-unit variation has the greater e ect, a circuit that has been desensitized to such variation is also insensitive to the e ect of temperature on . The design must, however, directly compensate for the e ects of temperature on leakage current ICBO (which doubles for each 108C rise in temperature) and base-to-emitter voltage VBEQ (which decreases approximately 1.6 mV for each 18C temperature increase in Ge devices, and approximately 2 mV for each 18C rise in Si devices). Constant-Base-Current Bias The constant-base-current bias arrangement of Fig. 3-14 has the advantage of high current gain; however, the sensitivity of its Q point to changes in limits is usage.
Example 5.1. The Si transistor of Fig. 3-14 is biased for constant base current. Neglect leakage current ICBO , and let VCC 15 V, RB 500 k, and RC 5 k. Find ICQ and VCEQ (a) if 50, and (b) if 100. (a) By KVL, VCC VBEQ IBQ RB 5:1
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CHAP. 5]
TRANSISTOR BIAS CONSIDERATIONS
Since IBQ ICQ = , we may write, using (5.1), ICQ IBQ so that, by KVL, VCEQ VCC ICQ RC 15 1:43 5 7:85 V (b) With changed to 100, (5.2) gives ICQ and, from (5.3), VCEQ 15 2:86 5 0:7 V 100 15 0:7 2:86 mA 500 103 5:3 VCC VBEQ 50 15 0:7 1:43 mA RB 500 103 5:2
Note that, in this example, the collector current ICQ doubled with the doubling of , and the Q point moved from near the middle of the dc load line to near the saturation region.
Example 5.2. Show that, in the circuit of Fig. 3-14, ICQ varies linearly with even if leakage current is not neglected, provided ) 1. Using the result of Problem 3.36(a) and KVL, we have IBQ RB ICQ 1 ICBO RB VCC VBEQ
Rearranging and assuming ) 1 lead to the desired result: ICQ VCC VBEQ 1 VCC VBEQ ICBO % ICBO RB RB
Constant-Emitter-Current Bias In the CE ampli er circuit of Fig. 5-1, the leakage current is explicitly modeled as a current source.
4 RC ICQ 3 IBQ 2 RB + VBB _ 1 RE 0 CE ICBO + VCC
IEQ 5
Fig. 5-1 Example 5.3. Use the circuit of Fig. 5-1 to show that (3.8) is the condition for -independent bias even when leakage current is not neglected. By KVL, VBB IBQ RB VBEQ IEQ RE 5:4
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