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TRANSISTOR BIAS CONSIDERATIONS
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Fig. 5-5 unit variation of rather than temperature that is of concern. However, the plot shows that the value of VBEQ does change signi cantly with temperature as claimed in Section 5.2.
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If the transistor of Problem 5.4 is supplied by a constant base current IBEQ 75 A, use SPICE methods to let range from 50 to 200 and plot the resulting collector characteristics to show the impact of unit-to-unit variations in .
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The netlist code below sets as a parameter to range from 50 to 200 in increments of 50.
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Prb5_5.CIR .PARAM Beta=0 Ib 0 1 75uA Q 2 1 0 QNPNG VC 2 0 0V .MODEL QNPNG NPN(Is=10fA Ikf=150mA Isc=10fA Bf={Beta} + Br=3 Rb=1ohm Rc=1ohm Va=75V Cjc=10pF Cje=15pF) .DC VC 0V 15V 1V PARAM Beta 50 200 50 .PROBE .END
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After executing hPrb5_5.CIRi, the plot of Fig. 5-6 is made using the Probe feature of PSpice. Inspection of the resulting plot shows that for a particular value of VCEQ and IBQ , the collector current ICQ varies nearly directly with ; thus, the conclusion of Example 5.2 is substantiated by numerical example.
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The transistor in the circuit of Fig. 3-19 is a Si device with ICEO % 0. Let VCC 18 V, VEE 4 V, RE 2 k; RC 6 k, and RB 25 k. Find ICQ and VCEQ (a) for 50 and (b) for 100.
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(a) By KVL around the base-emitter loop, VEE VBEQ IBQ RB IEQ RE We let IBQ ICQ = and IEQ ICQ 1 = in (1) and rearrange to obtain 1
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TRANSISTOR BIAS CONSIDERATIONS
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[CHAP. 5
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Fig. 5-6
ICQ
VEE VBEQ 4 0:7 1:3 mA RB 1 25 103 51 RE 2 103 50 50
Then KVL around the collector loop with IEQ ICQ 1 = yields     1 51 RE ICQ 18 4 6 2 1:3 11:55 V VCEQ VCC VEE RC 50 (b) For 100, ICQ VCEQ 4 0:7 1:45 mA 25 103 =100 101=100 2 103   101 18 4 6 2 1:45 10:37 V 100
In the circuit of Fig. 3-19, under what condition will the bias current ICQ be practically independent of if ICEO % 0
With ) 1, the expression for ICQ from Problem 5.6 gives ICQ VEE VBEQ VEE VBEQ % RB RB 1 RE RE
It is apparent that ICQ is practically independent of if RB = ( RE . The inequality is generally considered to be satis ed if RB RE =10.
In the circuit of Fig. 3-23, the Si transistor has negligible leakage current, VCC 15 V; VEE 5 V, RE 3 k, and RC 7 k. Find ICQ ; IBQ , and VCEQ if (a) 50 and (b) 100.
CHAP. 5]
TRANSISTOR BIAS CONSIDERATIONS
(a) KVL around the base loop yields IEQ Now, and ICQ IBQ VEE VBEQ 4 0:7 1:1 mA RE 3 103 50 I 1:1 1:078 mA 1 EQ 51 ICQ 1:078 10 3 21:56 A 50
and KVL around the collector loop gives VCEQ VCC VEE IEQ RE ICQ RC 15 5 1:1 3 1:078 7 9:154 V (b) For 100; IEQ is unchanged. ICQ IBQ and VCEQ However,
100 1:1 1:089 mA 101 1:089 10 3 10:89 A 100 15 5 1:1 3 1:089 7 9:077 V
In the circuit of Fig. 3-14, let VCC 15 V; RB 500 k, and RC 5 k. Assume a Si transistor with ICBO % 0. (a) Find the sensitivity factor S and use it to calculate the change in ICQ when changes from 50 to 100. (b) Compare your result with that of Example 5.1.
(a) By KVL, VCC VBEQ IBQ RB VBEQ so that and by (5.10), S @ICQ VCC VBEQ 15 0:7 28:6 10 6 @ RB 500 103 ICQ VCC VBEQ RB ICQ RB
According to (5.13), the change in ICQ due to alone is ICQ % S 28:6 10 6 100 50 1:43 mA (b) From Example 5.1, we have ICQ ICQ j 100 ICQ j 50 2:86 1:43 1:43 mA Because ICQ is of the rst degree in , (5.13) produces the exact change.
For the ampli er of Fig. 3-8, (a) nd the sensitivity factor and (b) show that the condition under which the sensitivity factor is reduced to zero is identical to the condition under which the emitter current bias is constant.
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