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Fig. 5-14 (b) For IDQ IDQ max , KVL requires that VDSQ max VDD IDQ max RD 15 5:5 2:5 1:25 V And, for IDQ min , VDSQ min VDD IDQ min RD 15 1:3 2:5 11:75 V
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The spread in FET parameters (and thus in transfer characteristics) makes the xed-bias technique an undesirable one: The value of the Q-point drain current can vary from near the ohmic region to near the cuto region.
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The self-biased JFET of Fig. 4-19 has a set of worst-case shorted-gate parameters that yield the plots of Fig. 5-15. Let VDD 24 V; RD 3 k; RS 1 k; and RG 10 M. (a) Find the range of IDQ that can be expected. (b) Find the range of VDSQ that can be expected. (c) Discuss the idea of reducing IDQ variation by increasing the value of RS .
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(a) Since VGG 0, the transfer bias line must pass through the origin of the transfer characteristics plot, and its slope is 1=RS (solid line in Fig. 5-15). From the intersections of the transfer bias line and the transfer characteristics, we see that IDQ max % 2:5 mA and IDQ min % 1:2 mA.
iD, mA
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RS = 3k
2.5 mA 1 2000
1.2 mA
LGS, V
Fig. 5-15 (b) For IDQ IDQ max , KVL requires that VDSQ max VDD IDQ max RS RD 24 2:5 1 3 14 V And, for IDQ min , VDSQ min VDD IDQ min RS RD 24 1:2 1 3 19:2 V (c) The transfer bias lines for RS 2 k and 3 k are also plotted on Fig. 5-15 (dashed lines). An increase in RS obviously does decrease the di erence between IDQ max and IDQ min ; however, in the process IDQ is reduced to quite low values, so that operation is on the nonlinear portion of the drain characteristics near the ohmic region where appreciable signal distortion results. But if self-bias with an external source is utilized (see Problems 5.27 and 5.48), the transfer bias line can be given a small negative slope without forcing IDQ to approach zero.
In the JFET circuit of Fig. 4-5(a), using self-bias with an external source, VDD 24 V and RS 3 k. The JFET is characterized by worst-case shorted-gate parameters that result in
TRANSISTOR BIAS CONSIDERATIONS
[CHAP. 5
the transfer characteristics of Fig. 5-16. (a) Find the range of IDQ that can be expected if R1 1 M and R2 3 M. (b) Find the range of IDQ that can be expected if R1 1 M and R2 7 M. (c) Discuss the signi cance of the results of parts a and b.
iD, mA
2.8 mA 2.2 mA 1.9 mA
1.3 mA
LGS, V
Fig. 5-16
(a) By (4.3), VGG R1 1 24 6 V V R1 R2 DD 1 3
In this case the transfer bias line, shown on Fig. 5-16, has abscissa intercept vGS VGG 6 V and slope 1=RS . The range of IDQ is determined by the intersections of the transfer bias line and the transfer characteristics: IDQ max % 2:8 mA and IDQ min % 2:2 mA. (b) Again by (4.3), VGG 1 24 3 V 1 7
The transfer bias line for this case is also drawn on Fig. 5-16; it has abscissa intercept vGS VGG 3 V and slope 1=RS . Here IDQ max % 1:9 mA and IDQ min % 1:3 mA. (c) We changed VGG by altering the R1 -R2 voltage divider. This allowed us to maintain a small negative slope on the transfer bias line (and, thus, a small di erence IDQ max IDQ min while shifting the range of IDQ .
The MOSFET of Fig. 4-18 is an enhancement-mode device with worst-case shorted-gate parameters as follows:
Value maximum minimum ID on , mA 8 4 VT , V 4 2
CHAP. 5]
TRANSISTOR BIAS CONSIDERATIONS
These parameter values lead to the transfer characteristics of Fig. 5-17 because the device may be assumed to obey (4.6). Let VDD 24 V; R1 2 M; R2 2 M; RD 1 k; and RS 2 k. (a) Find the range of IDQ that can be expected. (b) Find the range of VDSQ to be expected. (c) Discuss a technique, suggested by parts a and b, for minimizing the range of IDQ for this model of MOSFET.
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