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The arithmetic and logic unit (ALU) is responsible for performing mathematical, logical, and comparison functions. The instruction set of a computer is the list of primitive operations that the computer hardware is wired to perform. Modern computers have between 50 and 200 machine instructions, and instructions fall into the categories of data movement, arithmetic operations, logical operations, control transfer, I/O, and comparisons. Most programmers today write in higher-level languages, and so are isolated from direct experience of the machine instruction set, but at the hardware level, the machine instruction set defines the capability of the computer. Main memory provides random access to data and instructions. Today all manufacturers measure memory with a count of 8-bit bytes. Most machines, regardless of 16-bit, 32-bit, or 64-bit word size, also offer byte addressability. Since access to memory takes longer than access to registers on the CPU itself, modern designs incorporate cache memory near the CPU to provide a copy of the contents of a section of main memory in order to obviate the need to read from main memory so frequently. Cache memory entails complexity to manage cache coherency, but it typically results in speedup of average memory access time by 50 percent. Input and output functions today are based on I/O controllers, which are small special-purpose computers built to control the details of the I/O device, and provide a local memory buffer for the information being transferred in or out. Computers today use an interrupt system to allow the CPU to process other work while I/O occurs under the supervision of the I/O controller. When the transfer is complete, the I/O controller notifies the CPU by generating an interrupt. A further improvement in I/O efficiency is direct memory access (DMA). A DMA controller is another special-purpose computer within the computer, and it shares access to main memory with the CPU. With DMA, the CPU does not even get involved in moving the data into or out of main memory. Once the CPU tells the DMA controller where the data reside and how much data to transfer, the DMA controller takes care of the entire task, and interrupts only when the entire task is complete. REVIEW QUESTIONS 3.1 Write the number 229 in base 2. 3.2 What is the base-10 value of 11100101 3.3 What are the units (values) of the first 3 columns in a base-8 (octal) number 3.4 What is the base-2 value of the base-8 (octal) number 377 3.5 Convert the following base-10 numbers to base 2: 37 470 1220 17 99 3.6 Convert the following base-2 numbers to base 10: 00000111 10101010 00111001 01010101 00110011 3.7 Assume a 16-bit signed integer data representation where the sign bit is the msb. a What is the largest positive number that can be represented b Write the number 17,440. c Write the number 20. d What is the largest negative number that can be represented 3.8 Using ASCII encoding, write the bytes to encode your initials in capital letters. Follow each letter with a period. 3.9 Referring to the list of Intel x86 instructions in this chapter, arrange a set of instructions to add the values stored in memory locations 50 and 51, and then to store the result in memory location 101. You need not
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show the bit pattern for each instruction; just use the mnemonics listed, followed in each case by the appropriate operand(s). 3.10 What Intel x86 instructions would you use to accomplish subtraction using 2 s complement addition This instruction set has a SUB instruction, but don t use that; write your own 2 s complement routine instead. 3.11 What are the advantages of a larger computer word size Are there disadvantages If so, what are the disadvantages 3.12 Assume that cache memory has an access time of 10 nanoseconds, while main memory has an access time of 100 nanoseconds. If the hit rate of the cache is .70 (i.e., 70 percent of the time, the value needed is already in the cache), what is the average access time to memory 3.13 Assume our 1 GHz computer, which averages 3 cycles per instruction, is connected to the Internet via a 10 Mbit connection (i.e., the line speed allows 10 million bits to pass every second). From the time the computer receives the first bit, how many instructions can the computer execute while waiting for a single 8-bit character to arrive 3.14 What complexity does DMA present to the management of cache memory 3.15 Discuss the concept of a memory hierarchy whereby memory closer to the CPU is faster, more expensive, and smaller than memory at the next level. Arrange the different types of memory we have discussed in such a hierarchy.
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