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IN IN GS VREF IC IC OSC1 OSC2 VSS
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Bias circuit Chip power Chip bias CHIP REF High group filter Zero Digital crossing detection detectors algorithm Low group filter To all chip clocks OSC1 OSC2 St/GT ST GT
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Figure 16-5 M8870 touch-tone decoder block diagram.
212 HAM RADIO REPEATER
TABLE 16-1 FLOW
TOUCH-TONE DECODING KEY OE Q4 Q3 Q2 Q1
FHIGH
697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941 Any
1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 1633 Any
1 2 3 4 5 6 7 8 9 0 * # A B C D Any
H H H H H H H H H H H H H H H H L
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 Z
0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 Z
0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 Z
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Z
One possible use for AUX1 might be to utilize an ISD 2590 voice message to announce the repeater highlights or special notes about the repeater. The diagram in Fig. 16-6 illustrates a simple circuit for using the voice message chip. The audio output from the voice message chip would have to be interfaced to the transmit audio J3-3, so that the voice message would go out over the air. Voice messages are recorded in the voice chip by using the REC pushbutton switch and the microphone at pins 17 and 18. The play pushbutton is tied to transistor Q4, through a small relay. The repeater controller will also accept a 5-V signal through an alarm switch contact to notify the control operator of someone possibly tampering with the repeater. Flood or water sensors could also be employed as an alarm input source. An optional external CTCSS or subaudible decoding board can be integrated into the repeater. A Circuit Specialist s TS-64 board is shown in the schematic at Fig. 16-7. The output of the CTCSS board can be connected to the repeater controller via R14 on pin P12 of the STAMP 2 microprocessor. Additional connections on the subaudible board are the 12V power source and ground. The yellow or the PL wire from the TS-64 board is connected according to the manufacturer of your transmitter. Note, JP7 must be bridged on the TS-64 board while JP1 through JP6 must be configured to the proper PL tone for your application. A normally open pushbutton system reset switch is shown at S2. This switch is connected to the reset or RST pin of the STAMP 2 in the event of a system lock-up problem, should it ever occur.
BASIC COMPONENTS 213
TABLE 16-2 NAME
M8870 TOUCH-TONE DECODER CHIP PINOUTS DESCRIPTION
FUNCTION
IN INGS Vref IC IC OCS1 OSC2 Vss OE Q1, Q2 Q3, Q4 StD
Noninverting input Inverting input Gain select Reference volts output Internal connection Internal connection Clock input Clock output Negative power 3-state output enable 3-state outputs 3-state outputs Delayed steering logic
Connections to the front-end amplifier Connections to the front-end amplifier Access to output of front-end amp for feedback resistor Nominal Vdd /2, may be used to bias the input at midrail Must be tied to Vss Must be tied to Vss 3.579-MHz-crystal between these pins/internal oscillator 3.579 MHz crystal between these pins/internal oscillator Normally connected to 0 V Logic high enables the outputs Q1 Q4/internal pull-up When enabled by OE, provides code to last valid digit pair When enabled by OE, provides code to last valid digit pair Logic high when received tone pair registered, output latch updated; returns to logic low when voltage on St/Gt falls below VTSt Logic high when the digital algorithm detects a recognizable tone pair; momentary loss of signal will cause Est to go to logic low Steering input/guard time output; a voltage greater than VTSt detected at St causes the device to register the detected tone pair and update output latch. A voltage less than VTSt frees the device to accept a new tone pair. The GT output acts to reset the external steering time constant.
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