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J1 S2 R1 C1 Phone line R2 Tip Ring
9 8 7
XM 5V XM C3
On R1 J3-10 J3-1 J3 U3 U4 J4-1 J4
DAA 5V O C5 I C4 9-12Vdc CH1817 bottom view
J4-10
Figure 20-3 Page-Alert circuit diagram.
BASIC COMPONENTS 267
TABLE 20-1 PIN NAME
STAMP 2 MICROPROCESSOR PINOUTS FUNCTION DESCRIPTION
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
SOU SIN ATN VSS P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 VDD
Serial out Serial out Attention Ground User I/O 0 User I/O 1 User I/O 2 User I/O 3 User I/O 4 User I/O 5 User I/O 6 User I/O 7 User I/O 8 User I/O 9 User I/O 10 User I/O 11 User I/O 12 User I/O 13 User I/O 14 User I/O 15 Regulator out Power in
Temporarily connects to PC s Rx Temporarily connects to PC s Tx Temporarily connects to PC s DTR Temporarily connects to PC s ground User ports that can be used for inputs or outputs
Output mode: Pins will source from VDD. Pins should not be allowed to source more than 20 mA or sink more than 25 mA. As groups, P0 P7 and P8 P15 should not be allowed to source more than 40 mA, or sink 50 mA.
Input mode: Pins are floating (less than 1- A leakage). The 0/logic threshold is approximately 1.4 V.
Note: To realize low power consumption during sleep, make sure that no pins are floating, causing erratic power drain. Either drive them to VSS or VDD, or program them as outputs that don t have to source current.
Output from 5-V regulator (Vin powered). Should not be allowed to source more than 50 mA, including P0 P15 loads. Power input (Vin not powered). Accepts 4.5 5.5 V. Current consumption is dependent on run/sleep mode and I/O. When low, all I/Os are inputs and program execution is suspended. When high, program executes from start. Goes low when VDD is less than 4 V or ATN is greater than 1.4 V. Pulled to VDD by a 4.7K resistor. May be monitored as a brownout/reset indicator. Can be pulled low externally (i.e., button to VSS) to force a reset. Do not drive high. Ground. Located next to Vin for easy battery backup. Input to 5-V regulator. Accepts 5.5 to 15 V. If power is applied directly to VDD, pin may be left unconnected.
Reset I/O
23 24
VSS VIN
Ground Regulator in
268 PAGE-ALERT
TABLE 20-2 PIN
PAGE-ALERT PINOUTS USED DESCRIPTION
FUNCTION
1 2 3 4
SOUT SIN ATN VSS
Serial output programming pin Serial input programming pin Serial DTR line programming pin Ground programming pin INPUTS
5 6 7 8
P0 P1 P2 P3
IN1 alarm input 1 IN2 alarm input 2 IN3 alarm input 3 IN4 alarm input 4
OUTPUTS
14 15 20 21 23 24
P9 P10 P15 VDD VSS Vin
OH DAA relay drive TX DAA audio output pin LED status 5 V from regulator System ground 5 15-V input power (not used in project)
recommended for this project in the event of a component failure at a later date. Observe the phone line connector and the screw terminal strip at one edge of the circuit board. Note the 10-position screw terminal strip at J4, which is connected to a 10-pin female header at J3. The 10-pin header J3 is used to accept the motion module or the temperature voltage level (TVL) add-on modules, or other expansion devices. Table 20-3 illustrates the pinouts for the screw terminal strip and the 10-pin header connections. Once the Page-Alert has been completed, recheck the component placement and your solder connections. Now you are now ready to power your Page-Alert unit. Locate a 12 15-Vdc power supply to power your Page-Alert. You can readily elect to utilize the ubiquitous 12-Vdc wall wart to power your Page-Alert; usually these power supplies are quite economical. The Page-Alert prototype is housed in an economical 4- by 5-in Pactec enclosure.
Programming the Page-Alert
The Page-Alert is initially programmed via pins 1 through 4. These pins are the serial input/output connections used to program the BS2. The RX line is shown at pin 1, while the TX line is at pin 2. A DTR line is provided at pin 3, and the ground is at pin 4.
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