Using and Testing the Saturable Core in Software

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Using and Testing the Saturable Core
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Saturable Core Test Circuit .TRAN .1US 50US 0 .1US .PROBE .PRINT TRAN V(3) V(6) I(VM1) V(4) R1 4 3 100 RL 2 0 50 X1 1 0 6 CORE Params: VSEC=25U IVSEC=-25U LMAG=10MHY + LSAT=20UHY FEDDY=25KHZ X3 3 0 2 0 XFMR Params: RATIO=.3 VM1 3 1 V2 4 0 PULSE -5 5 0US 0NS 0NS 25US Use the above statement for Square wave excitation V2 4 0 SIN 0 5 40K Use the above statement for Sin wave excitation Adjust Voltage levels to insure core saturation .END
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Saturable core test circuit schematic. I(V3) = I(VM1).
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The test circuit shown in Fig. 2.27 can be used to evaluate a saturable core model. Specify the core parameters in the curly braces and adjust the voltage levels in the V2 4 0 PULSE or V2 4 0 SIN statements to ensure that the core will saturate. You can use Eqs. (2.11) and (2.12) to get an idea of the voltage levels that are required in order to saturate the core. The .TRAN statement may also need adjustment, depending on the frequency that is speci ed by the V2 source. The core parameters must remain reasonable, or the simulation may fail. When the simulation is nished, you can plot V(5) versus I(VM1) ( ux versus current through the core) to obtain a B-H plot. An improved version of this model, adding low-frequency hysteresis [100, 101], is shown below.
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.SUBCKT CORE 1 2 3 DH1 1 9 DHYST DH2 2 9 DHYST IH1 9 1 {IHYST} IH2 9 2 {IHYST} F1 1 2 VM 1 G1 2 3 1 2 1 E1 4 2 3 2 1 VM 4 5 C1 3 2 {SVSEC/250} IC={IVSEC/SVSEC 250} RB 5 2 {LMAG 250/SVSEC} RS 5 6 {LSAT 250/SVSEC} VP 7 2 250 D1 6 7 DCLAMP VN 2 8 250 D2 8 6 DCLAMP E2 10 0 3 2 {SVSEC/250} .MODEL DHYST D .MODEL DCLAMP D(CJO={3 SVSEC/(250 REDDY)} + VJ=25) .ENDS
SPICE Modeling of Magnetic Components
where SVSEC IVSEC LMAG LSAT IHYST REDDY Volt-sec at saturation = BSAT AE N Volt-sec initial condition = B AE N Unsaturated inductance = o R N 2 AE /LM Saturated inductance = o N 2 AE / LM Magnetizing I @ 0 ux = H LM / N Eddy current loss resistance
SVSEC and IVSEC are based on peak ux values. LMAG: For an ungapped core, L = LM (total path around core); for a gapped core, R = 1, L = gap length, AE = core area (m2 ). LSAT: Use core dimensions but with R = 1. REDDY: Equals LMAG reactance when permeability versus frequency is 3 dB down. Magnetizing current associated with low-frequency hysteresis is provided by current sinks IH1/IH2. With no voltage across terminals 1 and 2, these currents circulate through their respective diodes, and the net terminal current is zero. When voltage is applied, the appropriate diode starts to block and its current sink becomes active.
SPICE 3 Compatible Core Model A magnetic core model has three major elements: permeability, hysteresis, and core loss. Unfortunately, both the permeability and the core loss are nonlinear functions. The models in this chapter properly represent the nonlinear permeability and the hysteresis. The core loss has not been modeled in this SPICE 3 version. The model is based upon the premise that a magnetic element is represented by an inductance. The inductance is related to the permeability and geometrical properties of the core. The current through the inductor can then be simply stated as I= 1 L Vdt
This function can be modeled as a simple integrator. To properly represent the B-H loop characteristics, the nonlinearities of the inductance need to be de ned. Fortunately, graphical data are available that provide the percentage of initial permeability versus DC bias for several core types. Using curve- tting techniques, the nonlinear permeability can be approximated in closed-loop form. The nonlinear permeability can then be used to modify the slope of the integrator. The resulting equation, which we
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