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Magnetic saturation, short circuit condition AC loop stability analysis
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introduced. Most of the newer pulse width modulators utilize current mode control (which we will cover later in this chapter). The pulse width modulator compares the output of an error ampli er (VC ) to a xed sawtooth waveform that has a lower voltage (VL) and has an upper voltage (VH ). The output of the IC is a duty cycle, which is used to turn the semiconductor switch on and off. The duty cycle can be calculated as D= VC VL VH VL
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The output of the converter is the average of the switch duty cycle. The converter output is then de ned as Vo = Vin D Combining these two equations, we can obtain the modulator transfer function as Vo = Vin (VC VL) VH VL
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Similarly, the input current can be modeled as Iin = Io D
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*Pulse Width Modulator .SUBCKT PWM 1 2 3 4 5 E1 6 2 POLY(2) 1 2 4 5 0 0 0 0 1 G1 1 2 POLY(2) 6 3 4 5 0 0 0 0 1K RP 1 2 1MEG RS 3 6 1M .ENDS
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Figure 4.2a Pulse width modulator (PWM) equivalent circuit. The dashed line indicates that the voltage V(4,5) controls the dependent sources G1 and E1.
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Figure 4.2a demonstrates the basic structure and operation of the state averaging PWM switch subcircuit [5,66]. This model replaces the pulse width modulator switches. In Fig. 4.2b, a DC analysis is performed, in which we sweep V2 from 0 to 1. This terminal is the duty cycle control, so we are sweeping the duty cycle from 0% to 100%. As we monitor the output voltage and the input current, we can see that the output voltage is equal to V1 D, and the input current is equal to I1 *D, which agrees with our simpli ed derivation above.
PWM: TO SIMULATE A VOLTAGE NODE CONVERTER .DC V2 0 1 .01 .PROBE .PRINT DC V(2) I(V1) X1 1 0 2 3 0 PWM V2 3 0 I1 2 0 1 V1 1 0 10 .END
Four
50.0M DC I(V1) 10.5 -1.05
DC V(2)
-501M 0 v2 V(2) I1 1 1.00
V1 10
I(V1) X1 PWM
Figure 4.2b
PWM subcircuit to sweep the duty cycle from 0% to 100%.
SG1524A Buck Regulator The PWM switch can easily be combined with a PWM IC model, such as the SG1524 pulse width modulator subcircuit, to simulate a complete voltage mode converter. The PWM switch represents the Vo = Vin D function, while the SG1524 subcircuit correctly models the modulator gain. The next example combines the SG1524A subcircuit with the PWM switch to model a voltage mode buck regulator (Fig. 4.3). The SG1524 model is parameterized, which makes it more exible. The parameters passed to the SG1524A subcircuit are
T=10 s TO=1 s TS=0.25 s EP=3.5 V EO=0.5 V Switching period Dead time Transistor storage time Peak saw voltage Minimum saw voltage
You can view the SMPS Book.LIB le on the enclosed CD to see how the parameters are utilized in the SG1524 subcircuit. The regulator model is extremely simple. The SG1524A subcircuit contains the error ampli er, reference, and comparator sections. The comparator compares the output of the error ampli er with a sawtooth and generates a resultant duty cycle. The duty cycle is modi ed by the storage time and dead time parameters, which are passed to the subcircuit.
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C4 1 6 R5 47K C2 .01U
8 9 11
R4 22K
V(9) COMP
12 2
C3 6.8N
R6 1.5K V1 12
L2 1 L1 100U
V2 AC
V(10)
C1 220U
R3 100
Comp
R7 .05 X2 PWM
5V Ref.
Osc.
R1 10K X1 SG1524A
1524BCK: TO MODEL A VOLTAGE MODE BUCK REGULATOR .OP .AC DEC 25 100HZ 1000KHZ .PROBE V(9)=COMP .PRINT AC V(10) VP(10) V(9) VP(9) X2 2 0 4 1 0 PWM V1 2 0 12 R1 3 5 10K L1 4 10 100U C1 10 13 220U R3 10 0 100 R4 7 6 22K R5 7 8 47K C2 8 9 .01U C3 7 12 6.8N L2 10 6 1 C4 6 11 1 V2 11 0 AC 1 R6 12 6 1.5K R7 13 0 .05 X1 7 5 9 1 3 SG1524A Params: T=10U TO=1U TS=.25U EP=3.5 EO=.5 .END
Schematic and top-level netlist of a complete voltage mode converter using the PWM switch and SG1524.
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