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R1 RB
Buck mode converter with the addition of an external ramp.
Voltage Mode Control If we use a further extension of the circuitshown in Fig. 4.13, voltage mode control (also called duty cycle control) can be implemented. In this case, there is no current sensed, so that RB will ideally be set to zero. RB cannot be set to zero because it will result in a divide-by-zero error within the subcircuit. It may, however, be set to a very low value such as 1 m or less, if necessary. If we set K to 1, the result will be a duty cycle that is equal to the control voltage VC . The modulator gain can also be represented in this subcircuit by setting K to 1/Vr , where Vr is the peak-to-peak voltage of the ramp. Within the subcircuit, VC is bounded between 0 and 1 V. In order to use this limiting function, it is recommended that you set K to 1 and add the modulator gain externally.
V(15) VIN V(6) D B4 K*D V(5) VC
1:NP
V(11) VOUT
10 11
DELAY
CLK Q Q D R S
1:NC
1 2 16
V(9) D
R1 RB
Implementation of the external slope compensation ramp to the subcircuit.
Buck Topology Converters
R3 22K
L2 1 C5 1 R5 1.5K
R4 47K
C2 .01U
10 2
V(2) COMP
C3 6.8N
V2 AC E/A Comp
B1 V=V(14)
R1 10K
5V Ref. X1 SG1524A
Osc.
X3 SSFWD FORWARD
L1 100U VOUT
6 15
V(15)
VIN V1 12 VC
DUTY
C1 220U
R2 100
R6 .05
The buck mode subcircuit (forward) is used in a buck regulator simulation.
Improved SG1524A Buck Regulator The example in Fig. 4.14 uses the buck mode subcircuit to model the buck regulator example (Fig. 4.3).
1524BCK3: A NEW BUCK MODE SUBCIRCUIT .AC DEC 25 100HZ 1000KHZ V(2)=COMP .PRINT AC V(15) VP(15) V(2) VP(2) .PROBE V1 5 0 12 R1 4 7 10K L1 6 15 100U C1 15 8 220U R2 15 0 100 R3 1 9 22K R4 1 10 47K C2 10 2 .01U C3 1 11 6.8N L2 9 15 1 V2 12 0 AC 1 R5 11 9 1.5K R6 8 0 .05 X3 5 0 3 6 14 SSFWD Params: L=100U NC=1 NP=1 F=100K DMAX=.9 + RB=1M TS=.25U EB1 13 3 Value={ V(14) } C5 9 12 1 X1 1 7 2 13 4 SG1524A Params: T=10U TO=1U TS=.25U EP=3.5 EO=.5 .END
Four
Open Loop Gain (wfm1) in dB (Volts)
Phase (wfm2) in Deg
100K
Frequency in Hz 50mA Load
Graph of the open-loop gain and phase, node 15.
Open Loop Gain (wfm1) in dB (Volts)
Phase (wfm2) in Deg
100K
Frequency in Hz 50mA Load
Graph of the open-loop gain and phase with a 50-mA load.
Buck Topology Converters
The results of the simulation are shown in Fig. 4.15. Note the excellent agreement between this model and the previously used PWM switch model. The circuit was resimulated with a 50-mA load current, which caused it to operate in discontinuous conduction mode. The results of the simulation are shown in Fig. 4.16. Note the drastic difference in the phase gain plot compared with that of the PWM switch. The improved model correctly shows the reduction in modulator gain and also correctly shows that the modulator is represented by a single pole rather than two poles, as in the continuous conduction mode. From the operating voltages in the schematic, it is also evident that the improved model correctly shows that the duty cycle is signi cantly reduced as a result of the discontinuous operation. The graph in Fig. 4.17 shows the result of the modulator gain using the improved model.
Transient Model The Power IC Model Library for PSpice also includes transient-based models of many pulse width modulators, including the UC1524A, which is identical to the SG1524A. The next example shows the application of the nonlinear switching transient models to simulate the previous
Modulator Gain (wfm1) in dB (Volts)
Modulator Phase (wfm2) in Deg
100K
Frequency in Hz
Result of the modulator gain using the new model.
Four
Tran V(18) 493M
5.10 5.09 1.97M time 2.00M V(18) OUT
Tran ISWICH -6.54
X3 MTM8P10 1.97M time 2.00M I(V1) ISWICH V1 12 Q1 QN2222A 7 8 C6 .01U
L1 100U 6 D2 SHD1352
C2 220U
R5 1
I1 PULSE
R8 1.5K 17 C4 6.8N
C5 .047U R7 22K
R3 1K R2 10K R9 47
12 5 INV NINV 1 SYNC +CL 4 VREF 10 VIN EB CB 9 CA EA SD 14 GND COMP
D1 DN4148 R10 4.7
R4 .05
R6 47K 13 C3 .01U R1 3K
V(9) DRIVE
13.4 Tran DRIVE -590M 1.97M time 2.00M
-CL 2 3 RT CT
C1 2.2N
Tran COMP V(14) COMP
2.05 1.90 1.97M time 2.00M
Application of the transient subcircuits to simulate the previous buck
regulator.
buck regulator circuit (Fig. 4.18). The transient model properly models the output ripple, propagation delay times, and cycle-by-cycle switching effects. The disadvantage to the transient models is the increased simulation time and the dif culty in simulating frequency domain characteristics such as phase-gain analysis and audio susceptibility.
TRAN1524: TO SHOW THE APPLICATION OF THE TRANSIENT SUBCIRCUIT .TRAN .2U 10M 5M .05U UIC ; Load Step .TRAN .2U 5M 0 .05U UIC ; Startup .PROBE .OPTION GMIN=1N ABSTOL=10U VNTOL=10U RELTOL=.01 ITL4=100 V(6)=SWITCH V(15)=OUT I(V1)=ISWICH V(9)=DRIVE V(14)=COMP .PRINT TRAN V(6) V(15) I(V1) V(9) .PRINT TRAN V(14) R1 2 0 3K C1 3 0 2.2N R2 5 4 10K V1 10 0 12 Q1 10 8 7 QN2222A R3 10 8 1K D1 7 8 DN4148 D2 0 6 SHD1352 L1 6 15 100U C2 15 11 220U
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