Wfm2: Phase in Deg in Software

Generate QR Code ISO/IEC18004 in Software Wfm2: Phase in Deg

0 -100.000

100K

Wfm1: Gain in dB (Volts)

90.000 -40.000

0 -80.000

100K

Figure 5.4 Gain-phase Bode plot of the dual-output yback converter with a 30-mA load on each output.

Attenuation in dB (Volts)

-90.0 1

100K

460M

420M

380M

340M

300M

Feedforward Improvements The yback converter has a peak input current that varies with input voltage. This can be seen by sweeping the input voltage and monitoring the control voltage or the output of the error ampli er (see Fig. 5.6). Although this curve is not linear, the audio susceptibility of the yback converter can still bene t from feedforward compensation. This is most easily added via a simple resistor connected from the input voltage to the current sense pin of the PWM IC. We can add a feedforward signal in series with the control pin of the subcircuit to accomplish the same effect. The schematic showing the incorporation of the feedforward signal is shown in Fig. 5.7. The improvement in audio susceptibility is graphically shown in Fig. 5.8. Note that the feedforward signal improves the audio susceptibility performance by more than 20 dB. In several applications, I have been able to use this feedforward technique, rather than adding a linear regulator, to obtain the necessary attenuation. There are several bene ts. There is no reduction in ef ciency performance, as would occur with the addition of a linear regulator. Also, the converter can be made smaller and less expensively without the linear regulator.

R1 15

R2 15 V(18) -15

X5 TURNS D2 DN5806 -14.9 Tran -15 -15.0

V3 15

FLY2: FEEDFORWARD SIGNAL .OPTION GMIN=10N .NODESET V(2) = 15.7 .TRAN 10U 4M 2m 10u .PROBE .AC DEC 25 100 1MEG ALIAS V(11)=+15 ALIAS V(3)=SENSE ALIAS V(6)=FDBCK ALIAS V(18)=-15 ALIAS V(5)=D .PRINT AC V(6) VP(6) .PRINT AC V(11) VP(11) V(3) .PRINT TRAN V(3) V(18) V(5) V1 1 0 28 AC 1 X3 2 0 13 4 TURNS Params: NUM=18 X4 9 0 13 4 TURNS Params: NUM=18 X5 0 7 13 4 TURNS Params: NUM=18 X6 3 0 13 4 TURNS Params: NUM=12 D1 9 11 DN5806 D2 18 7 DN5806 C1 11 0 100U C2 0 18 100U I1 0 11 pulse 0 0.5 .1u .1u .1u 1m 2m ; use for load step analysis R1 11 0 15 R2 0 18 15 R3 4 0 1MEG X7 8 21 0 6 16 14 UC1843AS R4 3 21 8K R5 21 0 2.5K

C3 8 12 1N R6 12 21 47K V3 16 0 15 EB1 6 17 Value= { .005*V(1)} X1 1 0 17 2 5 FLYBACK Params: L=20U NC=100 NP=1 F=250K EFF=1 RB=10 + TS=.25U .END

(Continued).

Flyback Transient Response The transient response of the yback converter is unaffected by the addition of the feedforward signal. The transient response simulation results in Fig. 5.9 show an overlay of a 0.5-A step on the +15-V output with and without the feedforward signal. To calculate the DC output resistance, we use the following equations: Il = Ipk = 15 0.64 25 250 kHz Iout + D = 1.536 A

W2:With .005*Vin feedforward in dB (Volts)

W1:Without Feedforward in dB (Volts)

100K

2.2000M

2.6000M

3.0000M

3.4000M

3.8000M

0.1 + 1.15

The resulting 0.6 is a good approximation of the DC output resistance. Based on our example, the load regulation from 10% to 100% load would be V = 0.833 0.9 0.6 = 0.45 V The actual value that was recorded for the converter was 0.49 V. Obviously, the resistance is nonlinear and dependent upon input voltage, but this is a good estimate. The calculated output resistance was implemented into this SPICE model in order to get the simulation results of Fig. 5.11.