barcode in vb.net 2005 Improving Simulation Performance in Software

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Improving Simulation Performance
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C3 22U V(7) VDS
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L1 100U
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R1 10
R4 .1
V(10) GATE V3 PULSE
Circuit using a switch (voltage-controlled resistor) subcircuit for the MOSFET representation.
voltage, peak switch (or MOSFET) current, and the RMS switch (or MOSFET) current were recorded.
SEPIC1.cir .PROBE .TRAN .2u 2m 1900u .1u UIC .OPTIONS RELTOL=.001 C2 4 5 47U IC=24 C3 7 8 22U IC=24 R1 4 0 10 R2 5 0 .01 R3 8 2 2.2 R4 3 0 .1 L1 1 7 100U IC=2 L2 0 2 100U IC=3 X1 6 0 10 SWITCH V1 1 3 DC=24 V2 7 6 D1 2 4 DN5811 V3 10 0 PULSE 0 15 .1U .1U .1U 5U 10U C1 7 2 5U IC=24 .END
The circuit in Fig. 9.1 uses a switch subcircuit to represent the MOSFET. The circuit in Fig. 9.2 is an identical circuit, but it contains the MN6763 power MOSFET model. All the simulations were performed with SPICE 3 on a 75-MHz Pentium computer with 16 MB of RAM running under Windows 3.11 and
Nine
with PSpice on a 3-GHz Pentium 4 with 2 GB of RAM running under Windows XP. Needless to say, the 8 years between the rst version of this book and this version have seen a simulation speed increase (simulation time decrease) of over 40 times! The results are as follows: Switch Type RELTOL TSTEP( s) TMAX( s) Time (s) (PSpice) Time (s) Ripple (mVp p ) Peak switch current (A) RMS switch current (A) Switch Type RELTOL TSTEP( s) TMAX( s) Time (s) (PSpice) Time (s) Ripple (mVp p ) Peak switch current (A) RMS switch current (A) 0.001 0.1 0.2 4.27 191.50 319.94 6.07 3.57 0.001 0.1 0.2 0.94 35.40 388.59 6.22 3.65 Switch Subcircuit 0.01 0.1 0.2 0.7 34.70 452.71 6.22 3.65 0.01 0.1 none 0.38 14.38 453.16 6.23 3.60 0.01 0.2 none 0.34 13.68 417.12 6.23 3.71
MN6763 MOSFET 0.01 0.1 0.2 2.17 54.70 307.2 6.34 3.50 0.01 0.1 none 1.64 34.88 321.16 6.36 3.59 0.01 0.2 none 1.59 33.95 321.16 6.36 3.55
The typical graphs of the ripple voltage and switch current for the rst column of each simulation series are shown in Figs. 9.3 and 9.4. In the case of the switch subcircuit model, the error in the ripple voltage is due to a ring on the upper and lower peaks of the waveform. This appears to be related to aliasing of the waveform. A telltale sign of aliasing can be spotted if the waveform is clipped when it should be smooth. Here are some solutions to the aliasing problem: Tighten the maximum time step control (reduce TMAX). Take more data points (reduce TSTEP) if the waveform viewer is viewing interpolated data (output le data points) or TMAX if the viewer is viewing the noninterpolated internal data points from the simulator.
Improving Simulation Performance
C3 22U V(7) VDS
L1 100U
R3 2.2 C1 5U
V(2) VRECT D1 DN5811
V(4) VOUT C2 47U R1 10
V1 24
I(V2)
L2 100U
V(5) ESR R2 .01
R4 .1
V(9) GATE V3 PULSE
Circuit using a power MOSFET subcircuit to represent the MOSFET. The subcircuit is included on the enclosed CD.
16.0 24.3
Switch Current in Amps
VOUT in Volts Wfm1:
Wfm2:
-36.5M
1.91M
1.93M
1.95M
1.97M
1.99M
Time in Secs
Ripple voltage using the switch subcircuit.
Nine
Mosfet Current in Amps
VOUT in Volts Wfm1:
Wfm2:
1.91M
1.93M
1.95M
1.97M
1.99M
Time in Secs
x = 100U y = -9.27M
Ripple voltage using the MN6763 MOSFET subcircuit.
View the noninterpolated simulation data, as opposed to the interpolated .PRINT data that is based on the actual calculated time point values. Another possible cause is the spurious oscillations that can appear when trapezoidal integration is used. A solution to this phantom ringing problem is to use the Gear integration method rather than the trapezoidal integration method, which is the default for SPICE3. In general, the Gear method, in conjunction with a slightly reduced RELTOL value, yields simulation speeds that are similar to those of the trapezoidal method. Although the Gear integration method is somewhat slower, fewer time points will be rejected and therefore the total number of required time points will be reduced. PSpice uses a modi ed trapezoidal Gear method that is a combination of trapezoidal and Gear integration. This algorithm is always in effect and will tend to produce a response that is somewhere between what SPICE 3 will provide for either pure trapezoidal or pure Gear integration. The Gear integration method and the most liberal parameters (the last column) were selected, and the two circuits were simulated again. The results are provided below.
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