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Fig. 199
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* From section 9.5, a half-power frequency is a frequency at which the output power of a network is reduced to one-half its maximum value, being equivalent to 3 decibels. Or, in terms of VOLTAGE RATIO, by eq. (320), dB 20 log 0:707 3 decibels.
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CHAPTER 9 Impedance Transformation
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" " Inspection of the gure shows that jVo j Vi for ! 0; that is, jVo =Vi j 1 for ! 0. " Then, as ! is increased in value (Vi always remaining constant), the output jVo j decreases in value until the end of the passband is reached, which is generally taken to be the " frequency at which jVo =Vi j 0:707; this is the frequency at which the output is down 3 decibels from its maximum value. Next, as ! is further increased in value, we enter the transition band, as shown in the gure. The high-frequency end of the transition band can be taken as the frequency at " which jVo =Vi j 0:1, as shown above, which is the frequency at which the output is down 20 decibels from its maximum value. Beyond the transition band we enter the stopband, as shown. We assume that, for practical purposes, the output of the lter can be considered to be negligibly small for all frequencies in the stopband. We must remember that a low-pass lter is used in applications where it is desired to pass all signal components below a speci ed frequency and reject all components above that frequency. It therefore follows that the width of the transition band is especially critical, and should be as narrow as possible so as to prevent, as much as possible, the passage of unwanted higher frequency components through the lter. As you would expect, it s possible to design low-pass lters having frequency response curves GREATLY SUPERIOR to those of the simple RC and RL lters illustrated in Fig. 199. To do this requires the use of both inductance and capacitance (L and C), arranged in various ways, making use of the phenomenon of series and parallel resonance. One such arrangement is known as the constant-k type of lter, and is the subject of the next two sections. Before getting into these sections, however, we must rst take up the symmetrical T network, as follows. Let us begin by referring back to the standard T network notation of Fig. 174 in section 9.2. Let us then de ne that a symmetrical T network is a T network in which Z1 Z2 . Thus, Fig. 174 could be redrawn to represent a symmetrical T as shown in Fig. 200.
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Fig. 200
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Fig. 201
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Actually, however, the notation of Fig. 200 is not used in the SPECIAL CASE of the symmetrical T network; instead, it has become the custom to denote each of the series " " elements by Z1 =2 and the shunt element by Z2 , as shown in Fig. 201. This will cause no di culties so long as we remember that the special notation in Fig. 201 is to be used ONLY for the case of the symmetrical T network. In Fig. 201, terminals (1, 1) are given to be the INPUT terminals and (2, 2) the OUT" PUT terminals. Now suppose a load impedance ZL is connected to the output terminals in " Fig. 201; doing this will cause a certain value of INPUT IMPEDANCE, Zin , to appear at the input terminals as shown in Fig. 202. Note that, looking into terminals (1, 1) in Fig. 202, we see a series-parallel circuit " " " " consisting of Z1 =2 in series with the parallel combination of Z2 and (Z1 =2 ZL ). Thus
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