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CHAPTER 11 Matrix Algebra. Networks
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Fig. 295
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Fig. 296
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V will be equal to zero (that is, if we wish to be able to use the formulas found in section 11.9). In case an equivalent network cannot be found for which V 0, it is always possible, theoretically at least, to use one or more ideal transformers to insure that no undesired circulating current can ow in a proposed interconnection. This is illustrated in Fig. 297 for the series connection, where T is assumed to be an ideal transformer with 1:1 turns ratio.
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Fig. 297
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In regard to the transformer T, the impedance seen between the primary terminals is the same as the impedance seen looking into network a, because T is an ideal 1 to 1 transformer (section 10.6). Therefore, in Fig. 297, the input impedances to networks a and b are connected in series as far as an ac signal is concerned. Also, since T is an ideal 1:1 transformer, the same signal current I1 ows in both the primary and secondary sides. The important point to see now, in Fig. 297, is that the transformer forces the currents to be equal in both input terminals to network a, and hence no undesired loop current I3 can ow, as might be possible in Fig. 290, depending upon the nature of networks a and b. Transformer T in Fig. 297 must be as nearly ideal as possible. Whether or not this requirement can be met in a practical case will depend upon such factors as frequency, power level, cost, and limitations as to physical size.
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Matrix Algebra. Networks
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In closing, it should be noted that the problem of possible current imbalance does not arise in the cascade connection of two-ports, Fig. 288. Thus eq. (541) applies without reservation to the cascade connection.
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Let us begin by nding a matrix expression for a single shunt-connected impedance Z, which we can imagine to be the contents of the box of Fig. 277, as shown in Fig. 298.
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Fig. 298
In the gure we can, in principle, represent the contents of the box in terms of any one of the ve parameters z, y, h, g, or a, but here let us suppose we elect to use the zparameters. To do this we make use of the basic z-parameter equations, (494) and (495) in section 11.6, as follows, in which, from direct inspection of Fig. 298, we see that by eq: 494 for I2 0; by eq: 495 for I2 0; by eq: 494 for I1 0; by eq: 495 for I1 0; z11 V1 =I1 Z z21 V2 =I1 V1 =I1 Z z12 V1 =I2 V2 =I2 Z z22 V2 =I2 Z
and thus, for the single shunt impedance Z of Fig. 298, eqs. (494) and (495) become V1 ZI1 ZI2 V2 ZI1 ZI2 or, in matrix notation, V1 V2 ! ! !
I1 I2
Thus the matrix representation of a single shunt impedance Z, in the form of Fig. 298, is given by ! Z Z Z 543 Z Z Next, suppose the contents of the box in Fig. 277 consisted of a single seriesconnected impedance Z, as in Fig. 299.
CHAPTER 11 Matrix Algebra. Networks
Fig. 299
Now, in conformity with the notation used in the gure, we have, upon applying Ohm s law, viewed from terminals 1; 1 : I1 V1 V2 =Z V1 =Z V2 =Z viewed from terminals 2; 2 : I2 V2 V1 =Z V2 =Z V1 =Z Or, if we wish, since 1=Z Y the admittance of the series element, eqs. (500) and (501) become, for Fig. 299, I1 YV1 YV2 I2 YV1 YV2 or, in matrix notation, I1 I2 ! Y Y Y Y ! V1 V2 !
Thus the matrix representation of a single series impedance Z (or series admittance Y 1=Z) is given by ! Y Y Y 544 Y Y Next, let s nd the matrix representation for the case in which a transistor* is used with an unbypassed emitter impedance of Z ohms, as shown in Fig. 300.
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