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z 1 az 3 a2 z 5 a3 z 7 a4 z 9 z az 1 az 1 a2 z 3 a2 z 3 a2 z 3 a3 z 5 a3 z 5 a3 z 5 a4 z 7 a4 z 7
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Thus we have that F z 0 1 z 1 0 z 2 az 3 0 z 4 a2 z 5 0 z 6 a3 z 7 0 z 8 a4 z 9 which is in the form of eq. (583). The general statement in the time domain, eq. (584), is vs t v 0 d t v T d t T v 2T d t 2T v 3T d t 3T and thus, by direct comparison, the answers are v 0 0:000 v T 1:000 v 2T 0:000 v 3T a 0:450 v 4T 0:000 v 5T a2 0:203 v 6T 0:000 v 7T a3 0:091 v 8T 0:000 v 9T a4 0:041
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304. Referring to the notation in the generalized Fig. 346, we see that, in Fig. 345, b0 2, b1 3, b2 7, and a1 10. Hence, for Fig. 345, eq. (589) becomes Y z =X z H z 2 3z 1 7z 2 = 1 10z 1 ; answer: 305. The a coe cients in Fig. 346 would all be equal to zero, because a non-recursive processor uses no feedback; hence, for this type of processor, eq. (589) reduces to Y z =X z H z b0 b1 z 1 b2 z 2 bp z p ; answer: 306. From eq. (588) and Fig. 346, a processor is non-recursive if all the a coe cients are zero. Hence the answers here are (a) non-recursive, (b) non-recursive, (c) recursive.
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Comparison with eq. (588) shows that this is a purely non-recursive processor (no y nT qT terms on the right-hand side). Thus this is a non-recursive processor such as is illustrated in Fig. 343, but here requiring three delays. Hence the block diagram is as follows.
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(b) Since this is a purely non-recursive processor, all the a coe cients in eq. (589) are zero. Thus setting b0 4, b1 7, b2 5, and b3 9 in eq. (589), the answer is H z 4 7z 1 5z 2 9z 3 308. For q 4 in eq. (597) we have z 4 a1 z 3 a 2 z 2 a3 z a4 0 which, as explained in connection with eq. (602), possesses four poles. Since complex poles can occur only in the form of pairs of conjugate complex numbers, we have that the possibilities are (a) four real poles, or (b) two real and one pair of conjugate poles, or (c) two pairs of conjugate poles. 309. For q 5 in eq. (597) we have z 5 a1 z 4 a2 z 3 a3 z 2 a4 z a5 0 and hence, since a fth-degree equation possesses ve roots, the possibilities are (a) ve real poles, or (b) three real and one conjugate pair, or (c) one real and two conjugate pairs. 310. First, setting the numerator equal to zero, 4z 9 0, shows that H z has one zero, for z 9=4 2:25. Next, to nd the poles we set the denominator equal to zero and solve for z; thus z z 9 z2 5z 7 0 A
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which let us now put into the form of eq. (602), thus z z 9 z ha z hb 0 B
in which ha and hb are the two roots of the quadratic factor, which are, in this case, found by setting a 1, b 5, and c 7, into the standard quadratic formula which, as you should verify, yields the results ha 2:5 j 0:87 approx:; hb 2:5 j 0:87 approx: The advantage of putting eq. (A) into the form of (B) is that we can then see, by direct inspection of (B), that the FOUR POLES of H z are located at z 0 z 9 z ha 2:5 j 0:87 z hb 2:5 j 0:87
The above demonstrates that the most time-consuming part of such solutions lies in the necessity of factoring higher-degree expressions that may be present. 311. (a) The roots of the denominator, that is, the poles of H z , are, by inspection, located at z 0:46 and z 0:22. Thus, since both poles lie inside the unit circle, the processor is stable.
(b) The roots (poles) of H z are those values of z for which the denominator of H z is equal to zero. In this case, by inspection, we see that the rst pole is at z 0:61. Next, setting z2 1:6z 0:48 0 gives the two poles z 1:2 and z 0:4. Since the pole at z 1:2 lies outside the unit circle, the processor is unstable. (c) Let us rst write H z z 1:2 z 1:37z 0:305
which was obtained by multiplying the numerator and denominator of the given fraction by z2 . Then, setting the denominator z2 1:37z 0:305 0 gives the two roots (poles) z 1:09 and z 0:28. Since the pole at z 1:09 lies outside the unit circle, the processor is unstable. 312. Multiply the numerator and denominator by z 3 , thus getting, H z 2 4z 1 z 2 2 4z 1 z 2 ; answer: 1 5z 1 6z 2 9z 3 1 5z 1 6z 2 9z 3
313. The unit pulse response of a processor is the same as the transfer function of the processor (section 13.6). Since the processors are connected in cascade (series), we have (section 13.8) that H z H1 H2 H3 z3 z3 4 z 0:2 z 0:4 z2 0:8z 0:15 z 1:4z3 0:71z2 0:154z 0:012
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