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23-9 A family of characteristic curves for a hypothetical N-channel MOSFET.
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Common source circuit 425
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Depletion mode versus enhancement mode
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The JFET works by varying the width of the channel. Normally the channel is wide open; as the depletion region gets wider and wider, choking off the channel, the charge carriers are forced to pass through a narrower and narrower path. This is known as the depletion mode of operation for a field-effect transistor. A MOSFET can also be made to work in the depletion mode. The drawings and schematic symbols of Figs. 23-7 and 23-8 show depletion-mode MOSFETs. However, MOS technology also allows an entirely different means of operation. An enhancement-mode MOSFET normally has a pinched-off channel. It is necessary to apply a bias voltage, EG, to the gate so that a channel will form. If EG = 0 in such a MOSFET, that is, if the device is at zero bias, the drain current ID is zero when there is no signal input. The schematic symbols for N-channel and P-channel enhancement-mode devices are shown in Fig. 23-10. The vertical line is broken. This is how you can recognize an enhancement-mode device in circuit diagrams.
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23-10 Schematic symbols for enhancement-mode MOSFETs. At A, N-channel; at B, P-channel.
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Common-source circuit
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There are three different circuit hookups for FETs, just as there are for bipolar transistors. These three arrangements have the source, the gate, or the drain at signal ground. The common-source circuit places the source at signal ground. The input is at the base. The general configuration is shown in Fig. 23-11. An N-channel JFET is used here,
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426 The field-effect transistor but the device could be an N-channel, depletion-mode MOSFET and the circuit diagram would be the same. For an N-channel, enhancement-mode device, an extra resistor would be necessary, running from the gate to the positive power supply terminal. For P-channel devices, the supply would provide a negative, rather than a positive, voltage.
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23-11 Common-source circuit configuration.
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This circuit is an almost exact replica of the grounded-emitter bipolar arrangement. The only difference is the lack of a voltage-dividing network for bias on the control electrode. Capacitor C1 and resistor R1 place the source at signal ground while elevating this electrode above ground for dc. The ac signal enters through C2; resistor R2 adjusts the input impedance and provides bias for the gate. The ac signal passes out of the circuit through C3. Resistor R3 keeps the output signal from being shorted out through the power supply. The circuit of Fig. 23-11 is the basis for amplifiers and oscillators, especially at radio frequencies. The common-source arrangement provides the greatest gain of the three FET circuit configurations. The output is 180 degrees out of phase with the input.
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Common-gate circuit
The common-gate circuit (Fig. 23-12) has the gate at signal ground. The input is applied to the source. The illustration shows an N-channel JFET. For other types of FETs, the same considerations apply as described above for the common-source circuit. Enhancement-mode devices would require a resistor between the gate and the positive supply terminal (or the negative terminal if the MOSFET is P-channel).
Common draine circuit 427
23-12 Common-gate circuit configuration.
The dc bias for the common-gate circuit is basically the same as that for the common-source arrangement. But the signal follows a different path. The ac input signal enters through C1. Resistor R1 keeps the input from being shorted to ground. Gate bias is provided by R1 and R2; capacitor C2 places the gate at signal ground. In some common-gate circuits, the gate electrode is directly grounded, and components R2 and C2 are not used. The output leaves the circuit through C3. Resistor R3 keeps the output signal from being shorted through the power supply. The common-gate arrangement produces less gain than its common-source counterpart. But this is not all bad; a common-gate amplifier is very stable, and is not likely to break into unwanted oscillation. The output is in phase with the input.
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