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Common-drain circuit
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A common-drain circuit is shown in Fig. 23-13. This circuit has the collector at signal ground. It is sometimes called a source follower. The FET is biased in the same way as for the common-source and common-gate circuits. In the illustration, an N-channel JFET is shown, but any other kind of FET could be used, reversing the polarity for P-channel devices. Enhancement-mode MOSFETs would need a resistor between the gate and the positive supply terminal (or the negative terminal if the MOSFET is P-channel). The input signal passes through C2 to the gate. Resistors R1 and R2 provide gate bias. Resistor R3 limits the current. Capacitor C3 keeps the drain at signal ground. Fluctuating dc (the channel current) flows through R1 as a result of the input signal; this
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428 The field-effect transistor
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23-13
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Common-drain circuit configuration.
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causes a fluctuating dc voltage to appear across the resistor. The output is taken from the source, and its ac component passes through C1. The output of the common-drain circuit is in phase with the input. This scheme is the FET analog of the bipolar common-collector arrangement. The output impedance is rather low, making this circuit a good choice for broadband impedance matching.
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Table 23-1. Transistor circuit abbreviations.
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Base-emitter voltage Collector-emitter voltage Collector-base voltage Gate-source voltage Drain-source voltage Drain-gate voltage Emitter current Base current Collector current Source current Gate current Drain current
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*This is almost always insignificant.
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EB , VB , EBE , VBE EC , VC , ECE, VCE EBC, VBC, ECB, VCB EG, VG, EGS, VGS ED, VD, EDS, VDS EDG, VDG, EGD, VGD IE IB, IBE, IEB IC, ICE, IEC IS IG, IGS, ISG* ID, IDS, ISD
Quiz 429
A note about notation
In electronics, you ll encounter various different symbols that denote the same things. You might have already noticed that voltage is sometimes abbreviated by the letter E, and sometimes by the letter V. In bipolar and field-effect transistor circuits, you ll sometimes come across symbols like VCE and VGS; in this book they appear as EC and EG, respectively. Subscripts can be either uppercase or lowercase. Remember that, although notations vary, the individual letters almost always stand for the same things. A variable might be denoted in different ways, depending on the author or engineer; but it s rare for one notation to acquire multiple meanings. The most common sets of abbreviations from this chapter and chapter 22 are shown in Table 23-1. Wouldn t it be great if there were complete standardization in electronics And it would be wonderful if everything were standardized in all other aspects of life, too, would it not Or would it
Quiz
Refer to the text in this chapter if necessary. A good score is at least 18 correct. Answers are in the back of the book. 1. The current through the channel of a JFET is directly affected by all of the following except: A. Drain voltage. B. Transconductance. C. Gate voltage. D. Gate bias. 2. In an N-channel JFET, pinchoff occurs when the gate bias is: A. Slightly positive. B. Zero. C. Slightly negative. D. Very negative. 3. The current consists mainly of holes when a JFET: A. Has a P-type channel. B. Is forward-biased. C. Is zero-biased. D. Is reverse-biased. 4. A JFET might work better than a bipolar transistor in: A. A rectifier. B. A radio receiver. C. A filter. D. A transformer.
430 The field-effect transistor 5. In a P-channel JFET: A. The drain is forward-biased. B. The gate-source junction is forward biased. C. The drain is negative relative to the source. D. The gate must be at dc ground. 6. A JFET is sometimes biased at or beyond pinchoff in: A. A power amplifier. B. A rectifier. C. An oscillator. D. A weak-signal amplifier. 7. The gate of a JFET has: A. Forward bias. B. High impedance. C. Low reverse resistance. D. Low avalanche voltage.
8. A JFET circuit essentially never has: A. A pinched-off channel. B. Holes as the majority carriers. C. A forward-biased P-N junction. D. A high-input impedance.
9. When a JFET is pinched off: A. dID /dEG is very large with no signal. B. dID /dEG might vary considerably with no signal. C. dID /dEG is negative with no signal. D. dID /dEG is zero with no signal. 10. Transconductance is the ratio of: A. A change in drain voltage to a change in source voltage. B. A change in drain current to a change in gate voltage. C. A change in gate current to a change in source voltage. D. A change in drain current to a change in drain voltage. 11. Characteristic curves for JFETs generally show: A Drain voltage as a function of source current. B. Drain current as a function of gate current. C. Drain current as a function of drain voltage. D. Drain voltage as a function of gate current. 12. A disadvantage of a MOS component is that:
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