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Figure 3-46 M13 multiplexing process
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M01 1.544 Mbps
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24-DS-0s + framing bit
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4-DS-1s
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7-DS-2s
Figure 3-47 M12 frame has four subframes and 48-bit payload fields 1,176 bits
M 0 M 1 M 1 M 1
C 1 C 2 C 3 C 4
F 0 F 0 F 0 F 0
C 1 C 2 C 3 C 4
C 1 C 2 C 3 C 4
F 1 F 1 F 1 F 1
speeds differ slightly. This is unacceptable to a multiplexer which must rate align them if it is to properly multiplex them, beginning with the head of each signal. In order to do this, the multiplexer inserts additional bits, known as stuff bits, into the signal pattern at strategic places that serve to rate align the components. The structure of a bit-stuffed DS2 frame is shown in Figure 3-47; a DS3 frame is shown in Figure 3-48. The complexity of this process should now be fairly obvious to the reader. If we follow the left-to-right path shown in Figure 3-49, we see the rich complexity that suffuses the M13 signal-building process. Twentyfour 64 Kbps DS0s are aggregated at the ingress side of the T14 multiplexer, grouped into a T1 frame, and combined with a single frame bit to
The process is similar for the E1 hierarchy.
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Figure 3-48 M13 frame has seven subframes and 84bit payload fields 4,760 bits
X 1 X 1 P 1 P 2 M 1 M 2 M 3 F 1 F 1 F 1 F 1 F 1 F 1 F 1 C 1 C 1 C 1 C 1 C 1 C 1 C 1 F 0 F 0 F 0 F 0 F 0 F 0 F 0 C 2 C 2 C 2 C 2 C 2 C 2 C 2 F 0 F 0 F 0 F 0 F 0 F 0 F 0
3
C 3 C 3 C 3 C 3 C 3 C 3 C 3 F 1 F 1 F 1 F 1 F 1 F 1 F 1
Figure 3-49 The M13 multiplexing process and its complexity
M01 1.544 Mbps
Overhead Added
24-DS-0s + framing bit
6.312 Mbps
Overhead Added
4-DS-1s
44.736 Mbps
7-DS-2s
form an outbound 1.544 Mbps signal (I call this the M01 stage; that s my nomenclature, used for the sake of naming continuity). That signal then enters the intermediate M12 stage of the multiplexer, where it is combined (bit interleaved) with three others and a good dollop of alignment overhead to form a 6.312 Mbps DS2 signal. That DS2 then enters the M23 stage of the mux, where it is bit interleaved with six others and another scoop of overhead to create a DS3 signal. At this point, we have a relatively high-bandwidth circuit that is ready to be moved across the wide area network. Of course, as our friends in the UK are wont to say, there is always the inevitable spanner that gets tossed into the works (those of us on the left
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side of the Atlantic call it a wrench). Keep in mind that the 28- (do the math) bit-interleaved DS1s may well come from 28 different sources which means that they may well have 28 different destinations. This translates into the pre-SONET digital hierarchy s greatest weakness, and one of SONET s greatest advantages. In order to drop a DS1 at its intermediate destination, we have to bring the composite DS3 into a set of back-to-back DS3 multiplexers (sometimes called M13 multiplexers). There, the ingress mux removes the second set of overhead, finds the DS2 in which the DS1 we have to drop out is carried, removes its overhead, finds the right DS1, drops it out, and then rebuilds the DS3 frame including reconstruction of the overhead, before transmitting it on to its next destination. This process is complex, time consuming, and expensive. So, what if we could come up with a method for adding and dropping signal components that eliminated the M13 process entirely What if we could do it as simply as the process shown in Figure 3-50 We have. It s called SONET in North America, SDH in the rest of the world, and it dramatically simplifies the world of high-speed transport. SONET brings with it a subset of advantages that makes it stand above competitive technologies. These include mid-span meet, improved OAM&P, support for multipoint circuit configurations, unintrusive facility monitoring, and the ability to deploy a variety of new services. We will examine each of these in turn.
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