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FIGURE 23.5 The manufacturing flows for the two-major SLC manufacturing processes.
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Laser Via Technologies(3 5), [3 6], [7 10] Circled processes 3, 4, and 5, as well as squared 3 through 10 in Fig. 23.1, utilize a laser drill via generation technique. This process was first used in the late 1970s to drill small holes in G-10 laminate for buried vias in mainframe computer boards by IBM for its 3081 system and by Burroughs. (Attempts to find pictures of these products proved unfruitful.) The Hewlett
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FIGURE 23.6 Additional details of the SLC manufacturing process.
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FIGURE 23.7 A typical high-density DV Mult-PID board from NEC.
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FIGURE 23.8 The DV Mult-PID board manufacturing process.
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Packard laser-drilled Finstrate family of boards, first produced in 1983, is shown in 22. Siemens laser-drilled microwiring was produced since 1987. High-Density Interconnect (HDI). The HDI process developed by General Electric and now owned by Lockheed Martin is the one most similar to IC processes. This process is what is called a chips first, as the assembly is done before the substrate is completed and the IC bonding is direct to the substrate. It does not use flip-chip or wire bonding, but can utilize unmodified chips directly. A number of build-up layers and very fine geometry are possible. There are obvious advantages in making multichip modules and in using standard chips. The materials and bonding technologies have proven to be very reliable and suitable for military applications. The disadvantage is the maximum panel that can be sputtered. Future use of PVD/CVD metallization may make this process more cost-effective. Structure. The circuit structure of HDI consists essentially of common conventional flex circuits or more advanced microvia flex structures. These are purchased for this process. The polyimide film is usually 25- or 50-micron adhesiveness. The laser ablates away the polyimide to produce blind and through vias. The through vias are stopped by the aluminum bonding pads of the integrated circuits. By doing this, integrated circuits designed for wire bonding can be directly attached. Figure 23.9 shows a typical HDI structure. Manufacturing Process. The process starts with a finished single-sided, double-sided, or multilayer polyimide flex circuit.An adhesive is applied to the flex circuit.All the ICs and components are bonded to the polyimide film layer pair flex circuitry and cured. The assembly is turned over and a laser drills down through the flex circuitry to make blind and through vias including opening up the bonding pads on the IC chip. Gold, under-bump metallurgy, or C4 bumps are not required. The panel goes through tungsten sputtering to metalize the vias and seed the top layer. Circuit pattern can be applied, plated, and then etched to complete the circuit. The process is diagrammed in Fig. 23.10.10, 11
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FIGURE 23.9 Structure for the HDI multilayer substrate with lasered blind vias and direct connection to the ICs.
FIGURE 23.10 Manufacturing sequence for the HDI multilayer substrate with lasered blind vias. Meiko-BU. Meiko Circuits of Japan takes a photoresist and coats it onto a stainless steel panel. This starts the process to produce high density interconnect structures (HDIS) in a remarkable way. The advantages of this process is that surface geometries are not determined by etching or full additive metallization, the vias are under the surface lands, and the circuits are all flush with the dielectric, permitting the elimination of solder masks. On the negative side, this is a more expensive process that involves carriers.
FIGURE 23.11 The carrier-formed circuit multilayer structure. Structure. Figure 23.11 shows the structure of Meiko s build-up circuits.These are called carrier-formed because a stainless steel carrier serves as the base for the photodielectric even though they are laser-drilled to form the vias. The resulting structure is similar to other HDIs. The core is still a rigid board and the build-up layers are PID. Manufacturing Process. The manufacturing process (see in Fig. 23.12) starts by taking a photoresist and coating it onto a stainless steel panel. The surface pattern is exposed and developed in the photoresist. First gold is plated, then nickel, and finally copper is plated on the panel. When the resist is stripped, the PID is applied over the entire panel and via holes are laser-drilled in the dielectric. Once metalized and plated, photoresists can define the circuitry by etching. The process can be repeated until the circuitry is complete or it can be laminated to FR-4 materials as rigidizers.12 [13] CLLAVIS. The CLLAVIS build-up technology is marketed by CMK of Japan. This laser-drilled microvia technology is the most common of HDI processes. The cross-sectional view in Fig. 23.13 shows the filled buried vias in the multilayer core, as well as the optional filled microvias that can be stacked. This structure is also available with the simpler, unfilled staggered microvias. Manufacturing Process. The CLLAVIS manufacturing process is outlined in Fig. 23.14 and is identical to most of the laser-via-build-up technologies used. [14 28] SSP. The SSP technology was developed by Ibiden of Japan. It used standard FR-4, copper plating, and laser drilling. The additional step is the application of a thin adhesive to each finished single-sided, pump-plated core. The process sequence is as follows: 1. 2. 3. 4. 5. 6. Start with single-sided copper-clad laminate. Laser drill from the non-copper side. Desmear laser holes and run through the electroless copper process. Plate up bumps on the clad side. Image and circuitize the copper side. Apply a thin adhesive to the unclad side.
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