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FIGURE 23.23 The ALIVH-FB manufacturing process for a multilayer substrate. (Illustration Courtesy of CircuiTree.)
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23.3.2.10 MSF. Shinko of Japan developed the MSF HDI technology. It utilizes laserdrilled RCC materials and vias filled with a conductive paste. After testing, these are laminated into the parallel build-up structure. Figure 23.24 shows the typical manufacturing sequence for this HDI technology. 23.3.2.11 PALAP. PALAP (Patterned Prepreg Layup Process) is a process that was developed by a consortium consisting of the Japanese firms Denso, Wako Corporation, Airex, Kyosha, Noda Screen, and O.K. Print. Originally, the process started with copper-clad laminates (CCL), but now utilizes thermoplastics like PEEK resins (polyether-ether ketone) or a new plastic called PAL-CLAD. PAL-CLAD is characterized by the electrical properties and heat resistance of BIAC, a recyclable thermoplastic resin film produced by Japan Gore-Tex, Inc. The single-lamination process compares favorably to conventional PCB processing, where lamination, curing, and wiring patterning are repeated layer after layer. PALUP boards can be multilayered by pressing together all thermoplastic resin layers, each having wiring patterns, as shown in Fig. 23.25. This significantly improves quality, lowers costs, and shortens delivery times. PALAP boards also offer high-interconnecting reliability by adopting metallic paste for filling vias, and have excellent high-frequency properties due to a low dielectric constant.
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FIGURE 23.24 The MSF manufacturing sequence for a multilayer substrate.
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FIGURE 23.25 The PALAP manufacturing sequence for a multilayer substrate.
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FIGURE 23.26 The VIL manufacturing sequence for a multilayer substrate.
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PALAP boards also give due consideration to the environment, one of the major issues requiring action in the area of electronics products, including those used in information technology and automobiles. Because PALAP boards use thermoplastic resin as their base material, they enable material recycling in which only the resin is separated and reused. 23.3.2.12 VIL. The VIL (Victor Interconnected Layers) HDI technology was developed by Victor of Japan. It utilizes FR-4 prepreg materials that are laser-drilled and sequentially laminated after the vias are filled with a conductive paste. Figure 23.26 shows the typical manufacturing sequence for this HDI technology. 23.3.3 Mechanical Drill-Via Technologies (See Fig. 23.6) Hitachi HITAVIA is an example of the mechanical drill-via technologies available. 23.3.3.1 HITAVIA. The Hitachi HITAVIA technology is the only HDI process developed for use with conventional mechanical drilling. It utilizes RCC or prepreg materials that are mechanically drilled and sequentially laminated after the vias are filled with a conventional electroless copper and copper plating.The typical manufacturing sequence for this HDI technology is similar to that of previously described HDI processes such as CLLAVIS and PPBU. 23.3.4 Plasma-Via Technologies (See Fig. 23.7) Plasma-via technologies include DYCOstrate, plasma micromilling, and plasma-etched redistribution layers (PERL). 23.3.4.1 DYCOstrate. Starting in 1989, Dr. Walter Schmidt of Contraves in Switzerland developed the plasma-etching process for microvias. Evolving from the traditional plasma desmear process, the plasma etcher for vias was jointly developed by Dyconex (successor to Contraves) and Technic Plasma of Germany. Dyconex trademarked and patented its viageneration process as DYCOstrate. Hewlett Packard licensed the technology in 1993 and developed it for mass, low-cost production. The low-cost production process of Hewlett Packard is called PERL (for plasma-etched redistribution layers).
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FIGURE 23.27 The DYCOstrate multilayer structure and cross-sections of through and blind vias.
DYCOstrate, along with SLC and Finstrate, is among the most enduring production processes for microvias generation. The DYCOstrate process was first employed for highreliability military, aerospace, medical, and IC packaging starting in 1991. Since that time, Dyconex has used the process to produce hundreds of different printed boards both in polyimide film and with the new laminates called FR-4 RCC. This Dyconex called DYCOstrate-C. 23.3.4.1.1 Structure. Figure 23.27 shows the structure of DYCOstrate. The core material can be polyimide film with plasma-etched holes, drilled epoxy fiberglass, or other plasmaetchable materials such as liquid crystal polymers. Multiple layers can be built up to increase density with the resulting buried and blind vias, but two-sided DYCOstrate structures are also used in products because of the very high density that 0.075 mm through holes allow. 23.3.4.1.2 Manufacturing Process. The manufacturing process for a DYCOstrate substrate utilizes common printed circuit board techniques. Only the via-generation process is different. To produce a plasma-etched via hole, manufacturers use two or three process steps that replace the conventional mechanical drilling-debur-desmear steps: 1. Define photographically the location and geometry of the via holes. 2. Etch an opening in the copper foil that will serve as the resist mask. 3. For blind vias, reduce the copper-foil thickness to eliminate the copper overhang. Figure 23.27 shows microsections of a plated through hole and a blind via in polyimide film. The plasma-etch procedure is basically an isotropic process, as indicated by the undercut seen on the through hole; considering the actual dimensions, however, this undercut is too small to cause any plating problems. When the etching depth is increased, as in the case of a blind via, the resulting undercut is generally too big to allow reliable plating. To overcome this problem, the manufacturer can reduce copper use by etching the copper foil, eliminating the copper overhang, and providing a thinner copper foil for fine-line resolution. Figure 23.28 shows two common products made with the Dycostrate process (a four-layer flex-multilayer chip-on-board (COB) for a hearing aid) and the PERL process (a six-layer FR-4 COB for a networking module).
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