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technology called high-density interconnect, capable of 1.58-mil (40- m) lines and spaces have been developed.
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Electronic Packaging Issues and Concerns Electronic packaging begins where circuit design leaves off. 3.1.2.1 Physical Design and Packaging Issues. The issues involved in electronic physical design and packaging are as follows:
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Selection of appropriate electronic components (i.e., semiconductors, discrete, and passives) Mechanical layout and assembly of components, interconnectors, and cases Production engineering/technology Electrical parameters of interconnects (controlled-impedance design, cross talk, clock skew, signal propagation delay, electromagnetic interference for RF circuits, etc.) Thermal conditions (heat dissipation, cooling, etc.)
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3.1.2.2 Digital Circuit Design Considerations. Digital circuits should be able to do the following:
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Transfer a complete logic swing in shortest time Have the interconnect characteristic impedance designed to equal the load impedance Have characteristic impedance that is purely resistive to minimize reflections Accommodate clock skew
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For the interconnection of digital semiconductor devices, a major issue that must be considered is clock skew, which results from varying the length of clock lines and is a major design consideration for high-speed products. 3.1.2.3 Analog Circuit Design Considerations. Analog circuits should be able to do the following:
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Maximize power transferred from input to output Make the driver impedance a complex conjugate on the transmission line
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3.1.2.4 Power Issues for Silicon Semiconductors. The following items are power considerations for silicon semiconductors:
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Transistor-transistor logic and complementary metal oxide semiconductor (CMOS) power dissipation depend on frequency and increase dramatically at high frequencies. Drain of an emitter collector logic device is independent of frequency for a given load. Resistance loading drains the output capacitor of CMOS circuitry. Terminating CMOS circuits to control reflection imposes a power penalty.
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Gallium arsenide (GaAs) semiconductors are now technologically competitive with silicon,2 especially for high-speed logic applications. For GaAs logic, power dissipation is independent of frequency, and GaAs circuit operation is unaffected by power supply voltages down to about 1 V. 3.1.2.5 RF Semiconductors. GaAs bipolar CMOS and silicon germanium are semiconductor technologies now being used in RF circuits of many wireless products. Special attention
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is required in the packaging of RF components to control the electrical parasitics, the thermal resistance for components such as power amplifiers, etc.
Requirements for Electronic Systems The requirements for electronics systems and products driven by semiconductor technology developments are as follows: 1. The advances in integrated semiconductor technology mean products operate at higher speeds and have higher performance and greater functionality. 2. The reliability and quality of products are givens and are expected to be built in at no cost premium. 3. The volume (i.e., size) of the electronics products is diminishing, and is constrained only by ergonomic requirements and the ability to dissipate heat (i.e., power). 4. The costs of the components and assembly are expected to continuously decrease with time. 5. The time to market impacts all of the preceding items.
SINGLE-CHIP PACKAGING
Prior to 1980, the semiconductor package predominately used was the dual inline package (DIP). The package is rectangular in shape with leads on a 0.100-in pitch along the long sides of the package. Figure 3.4 shows the various semiconductor formats and package trends. The packages on the left side of Fig. 3.4 are essentially perimeter I/O packages i.e., DIPs, quad flat packages (QFPs), plastic leaded chip carriers (PLCCs, tape automated bonding (TAB), etc. The package types on the lower right side of Fig. 3.4 represent area array packages such as pin grid array (PGA) packages (an array of pins attached to the package base for electrical connection), land grid array packages (an array of conducting pads on the package base for electrical connection, sometimes called pad array carriers [PACs], or, when the lands have reflowed solder balls attached, ball grid array [BGA] packages), and multichip modules. The pitch of the I/Os of DIPs and PGA packages is 0.1 in, while the I/O pitches of the balance of the parts
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