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FIGURE 3.9 Perimeter I/O package vs. area array package.
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FIGURE 3.10 PAC packaging efficiency
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3.2.4.1 Perimeter Array I/O Package Advantages and Disadvantages Perimeter array I/O packages at 0.050-in pitch can be readily surface-mount assembled. Both 0.4-mm pitch perimeter I/O QFPs and 0.3-mm pitch perimeter I/O QFPs are now in manufacture. Reviewing Fig. 3.8, which shows QFP size versus lead pitch and pin count, it is apparent that the usefulness of QFPs is limited to around 400 I/Os. There still is a controversy in the packaging and assembly community as to whether 0.3-mm pitch QFPs, particularly with a large number of I/Os, are a high-throughput, high-assemblyyield part due to the fragility of the lead (0.015 mm wide) and the possibility of solder shorts between leads.
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3.2.4.2 Pad Array and BGA Packages. This disconnect is being addressed first by pad array and BGA package technology. References 5 and 6 provide details of this emerging technology, particularly as it relates to low-cost plastic array packages with reflowed solder balls attached to the package array I/Os. Figure 3.11 shows a ceramic BGA (CBGA) and Fig. 3.12 shows a cross section of the plastic BGA.
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FIGURE 3.11
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Ceramic ball grid array.
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FIGURE 3.12 Ball grid array cross section.
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The advantage of ball grid array packages (ceramic or plastic) include the following:
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The package offers a high-density interconnect. Pad array pitches of 1.27, 1.0, 0.8, and 0.5 mm are now commercially available. The packages have achieved six-sigma soldering (demonstrated for 1.27- and 1.00-mm I/O pitches) because of the large volume of solder on the I/O pad. The package is a low-profile part (package thicknesses as low as 1 mm are now available). The package has superior electrical performance in that the total lead length is short, controlled impedance interconnects can be designed in, and low-dielectric constant and lowloss materials can be used for the substrate. The package depending on the design has the potential for superior thermal performance. The package concept is extendable to multichip packages (MCPs).
Table 3.2 gives the expected ranges of I/O for BGA packages for high-end microprocessors and for dies used in portable products. In 2000, approximately 60 percent of all BGA packages
SEMICONDUC TOR PACKAGING TECHNOLOGY
had 1.27- or 1.00-mm pitch and the balance had 0.8- or 0.5-mm pitch. By 2004, 60 percent of all BGA packages will have 0.8- or 0.5-mm pitch, with a small number having less than 0.5-mm pitch.
TABLE 3.2 BGA Pin Counts Year Pin count, high-end logic Pin count, portable products 2001 700 1000 256 2005 1000 1900 312 2010 1200 4000 360
The area efficiency of BGA packages that have a relatively low pad count (i.e., less than 140) has increased in the last several years. This new form of the BGA package, called chipscale package (CSP), has an area efficiency of around 80 percent (i.e., 80 percent of the package area comprises the silicon die area). The pad pitch on CSPs range from 0.8 to 1 mm. CSPs should be considered a variant of the BGA package technology. Figure 3.13 shows a typical CSP package.
FIGURE 3.13 Typical CSP technology. (Courtesy of Amkor Inc.)
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A new and smaller package called a wafer-scale package (WSP) has been developed. Figure 3.14 shows such a package.The area efficiency of this package is 100 percent (i.e., 100 percent of the package area comprises the silicon die area). A WSP is a package where all the packaging processes are completed on the silicon wafer, including application of the I/O solder balls. The WSP has relatively low I/O count and has pad pitches ranging from 0.8 to 1 mm. Generally, a redistribution of the chip I/Os uniformly over the die area is required to obtain these pitches. The WSP requires no chip under encapsulation, as is required by direct chip attach (DCA), discussed in Sec. 3.2.5.
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