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FIGURE 27.12
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confirm the models predicted values by actual process verification. The most versatile method of verification is with a test coupon. The test coupon should accurately represent the construction configuration of the stack-up, except it requires a few special prerequisites in order to yield reliable test data. Figure 27.12 shows a typical impedance test coupon stack-up. Note that the signal reference planes of the coupon are shorted together.Also, the simulated signal line is isolated and open-ended; the signal lines are usually at least 6 in. long. The footprint of the coupon via holes that feed through to the surface should be verified to match to the spacing of the time domain reflectometry (TDR) instrument probe. This will reduce the risk of rendering the specimen not testable or necessitating the use of expensive adjustable probes. The IPC test method IPC-TM-650 contains suggested spacing, but it is best to confirm this with the manufacturer s preference. Examples of some common impedance types are shown in Fig. 27.13. The factors most influential on characteristic impedance are:
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Dielectric separation (H) The separation of the signal line between the reference planes has a significant influence on characteristic impedance. The variability of the dielectric layering must be reduced to minimize the effect on tolerance. This is where stack-up selection becomes critical when determining whether the signal-to-plane opening will be made with a clad laminate or within the bondable area of the B-staged (prepreg) resin. This is also where glass
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FIGURE 27.13 Examples of common impedance stacks.
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style selection becomes important. The glass style and subsequent resin content will have different effects on the nominal thickness obtained. Conductor width (W) The finished width of the conductor can produce variance, which is likely to occur from lot to lot. Therefore, process control measures are necessary when producing controlled impedance circuits. The density of neighboring circuits will have an effect on the final etch. Often it is advantageous to modify the artwork line width at phototool generation for predicted variance. Dielectric constant (Dk) Choosing a laminate resin system with a consistent dielectric constant has an influence on characteristic impedance over higher frequencies. The influence of dielectric constant becomes most critical when the ML-PWB design is a high-layer-count design. The lower the Dk value of the resin system, the thinner the overall board can be. Typically, the manufacturer has little opportunity to affect the dielectric constant, because the material type is specified by the design. Here, it is important that the designer/manufacturer know the Dk value range of the laminate supplier s resin system. Caution: Do not use the Dk value of the neat resin, but that of the composite laminate, which will vary somewhat with glass style. This is sometimes referred to as effective Dk (Eff Dk). Conductor thickness (T) The conductor thickness or copper weight can also affect the final impedance value. Here, as with conductor width, manufacturing process variations can have an inverse effect on the precision of the impedance value. Some modern software simulation tools, such as those from Polar Instruments, Inc., allow values for conductor profile (area) to be included in the simulation. This is more significant when lines are of heavy copper. It is best to avoid routing of impedance lines on plated subcores due to the added variability.
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For external impedance tracks and internal plated-up tracks such as on subcores, autothieving patterns will minimize large variations in plating height between tracks in dense areas and those in uncongested areas. This will increase the fabricator s ability to produce impedance values consistently within a smaller range. 27.3.4 Sequential Laminations When a design includes buried and/or blind vias, it typically requires a set of sequential lamination and plating cycles. These technologies are defined in the industry design standard IPC- 2221/2222 and are known as Type 4 ML-PWBs. These build types, when employing industry standard feature sizes, are mature in the industry. Complementing technologies, employing use of sequential processes for ML-PWB designs containing microvias less than 0.15 mm, are considered as build-up technologies. The terminology of build-up technologies encompasses many design stack-up variations; they can take on many forms and employ a multitude of methods. The build-up technologies defined in IPC-2315 and IPC-2221/2226 include categories named Type I, II, III, IV, V, and VI. The advanced build-up technologies use the materials found in IPC-4104. These include materials for layer forming, dielectric insulation, and interconnectivity. Included are photo-imageable and non-photo-imageable materials (liquid, paste, or dry-film nonreinforced dielectric); adhesive-coated dielectrics (reinforced and nonreinforced); and conductive foils and paste (coated and non-coated, photo-imageable). For a detailed discussion of these processes, see Chap. 22 and 23. This discussion will limit itself to addressing processes for standard technology Type 4 and advanced technology build-up Types I, II, and III, which can be manufactured with conventional processes. The Buried Via Stack-Up. To avoid hopelessly complex routing, each signal net is generally routed using only one pair of layers with what is called Manhattan geometry. This means that diagonal routing is avoided and all signal lines run in a horizontal or a vertical direction. To avoid blockage and side-to-side cross-talk problems, horizontal lines are run on
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