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To complicate the problem further, off-chip interconnects are beginning to contribute to the challenge of SOC integration. What this means is that interconnects, and not the ICs, are dominating, and often limiting, the system performance and increasing its cost.7 Consequently, there is mounting support for moving interconnects off the chip and onto the package.8 4.3.1 System-on-a-Chip (SOC) There are many reasons why semiconductor manufacturers continue to push on-chip integration of a system.9 The reason most often cited is that on-chip integration allows faster interconnection between circuit components simply because of the shorter distances involved. However, it has been pointed out that this may not be the case for all designs. For example, on a large digital IC running at a high clock frequency, a signal traveling on a global interconnection trace may take dozens of clock cycles to reach its destination. In such a case, dividing the device into smaller dice and using high-density interconnects on a package substrate can actually be faster.10 Another reason for continuing with on-chip system integration is to avoid the configuration of a multichip package (MCP) because, historically, packages containing a system composed of a multiple number of chips have been larger than those containing a single-chip system. Although designers will continue to be pressured to integrate as much functionality onto a single chip as possible, there are many factors that must be considered when deciding if SOC is the right approach to the design of an electronic system. Furthermore, as minimum geometries continue to shrink and chip sizes continue to increase due to the incorporation of additional functionality, a point may be reached where it becomes economically impractical, if not impossible, to fabricate SOC. At this point, SOP may provide the only practical alternative to SOC. Now that chip and package are starting to be codesigned, an opportunity exists to develop capabilities for designing the SOP solutions that would cost less and perform better than SOP solutions.11 Figure 4.2 provides a list of some of the challenges that must be addressed if SOC is to become the standard approach to electronic system integration.
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SOC Challenges Fundamental: latency, SiO2 insulation Process complexity SOC design and test Wafer fab costs and yields Intellectual property for integrated functions
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SOP Challenges Design: High speed digital, optical analog, RF Large-area intelligent manufacturing, cost/yield Thermal management Testing and reliability High performance for low cost fab
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FIGURE 4.2 Issues that must be addressed prior to full-scale implementation of SOC and SOP.
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System-on-a-Package (SOP) The definition of SOP depends on what is considered to be a system. In fact, much of what is referred to today as an electronic system is in reality a subsystem, meaning that it does not perform an autonomous electronic function. Consequently, SOP has multiple definitions. For example, some consider a multiple number of logic and memory ICs in a single package as an SOP. On the other hand, if the SOP does not contain analog peripheral device drivers, one might argue that the package really doesn t contain a system. Additionally, complete systems usually contain passive devices in addition to the ICs. Passive devices are required to make systems work, and if an entire system is to be placed in a package, then the required passives must go in as well,3, 11 making it what is often referred to an MCM. Area array packaging is becoming an enabling technology for addressing the needs of customized SOP solutions in order to reduce size, weight, and pincount at the second level of interconnection.12 This type of packaging technology includes pin grid array (PGA), ball grid array (BGA), and chip-scale packages (CSP), with BGA playing the largest role, primarily
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ADVANCED COMPONENT PACKAGING
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System Trends System
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Portability Wireless / Bluetooth High Performance Low Cost Diverse Functionality
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Ro ute
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C SO
Concurrent Engineering SOP Optimization
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Packaging Trends
Low Cost High Performance High Integration
IC Trends
Fine Lithography Large Die Expensive Fab Infrastructure Lower Yield / Higher Cost Complex Performance Challenges Reliability Challenges
FIGURE 4.3 Future trends of IC, packaging, and system technologies as envisioned by personnel of the Packaging Research Center at The Georgia Institute of Technology. (Drawing provided courtesy of the Packaging Research Center, the Georgia Institute of Technology.)
because of its versatility. Compared to conventional leaded packages, BGA packages exhibit improved electrical performance due to a shorter distance between the IC and the solder balls, improved thermal performance by the use of thermal vias or heat dissipation through power and ground planes, reduced handling related lead damage, and increased manufacturing yields due to their self-alignment feature.13 In fact, BGA has been one of the biggest contributing factors to the proliferation of mobile phones and other wireless communication systems. However, even with the advantages created by area-array packaging, performance, reliability, and cost requirements are challenging currently available area-array electronic package design, primarily by because of materials issues14 Fig. 4.3 provides an overview of IC, packaging, and system trends that are anticipated for the year 2007 and beyond.
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