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Efficiency of Electroless and Galvanic Plating PWB manufacturers which are not familiar with electroless plating often have the misconception that electroless plating takes too long. On the contrary, electroless plating is faster than galvanic plating, and its volumetric efficiency is twice as much as galvanic plating. Electroless plating baths operate at the speed of 2.0 to 5.0 mm/h, 2.5 mm being the medium speed. Because of its high throwing power, a deposition thickness of 25 mm on the panel surface also assures 25 mm in the hole. That is, 10 h are needed to plate this thickness. The loading factor in electroless plating can be maintained at 4 dm2/liter.A 2500-gal (10,000-l) tank can plate about 400 m2 (4000 ft2) of panels in one shot in 10 h.That is, 400 ft2/h, or approximately 130 (18-in 24in) panels/h from a 10-m3 tank.This is equivalent to twice the speed of galvanic plating from the same volume of plating solution. When small, high-aspect-ratio holes are involved, this figure becomes more favorable to electroless plating because the current density of galvanic plating must be reduced to 10 to 12 A/ft2, which requires more than 2 h of plating for 25 mm in the hole. Figure 31.7 shows the plating racks filled with panels waiting to be placed in electroless plating tanks. In large-volume operations, the panel-racking operation is fully automated.
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Photochemical Imaging Systems Various photochemical imaging systems have been developed and tried to be put into practice.6 However, no photochemical imaging systems are used for real production today. They are all unstable and the lateral growth of conductors poses a problem for the fineline applications for which they are intended.
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Molded Circuit Application A handful of three-dimensional molded circuit manufacturers (or, the preferred identification, molded interconnection device or MID) have continued their quest for market with this
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FIGURE 31.7
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Plating racks filled with panels to be plated. (Photo courtesy of Adiboard, Brazil.)
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product and have met with some success. (See Fig. 31.8.) There are several alternative methods to manufacture MIDs, of which the two-shot molding method can produce the most sophisticated three-dimensional interconnection devices. A part which is to be metallized (circuitized) is molded first. Then, a portion of the first mold which is not desired for metallization is surrounded by the second molding, exposing
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FIGURE 31.8 An example of a three-dimensional molded circuit application, in this case a light pen for computer input. (Photo courtesy of Mitsui Pathtek.)
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only the portion desired to be metallized. This two-shot molding method can be classified further into two alternative methods, which are similar to CC-4 and AP-II. One is to use catalyzed engineering plastic for the first molding and noncatalyzed plastic for the second molding. Adhesion promotion consists of a swell-and-etch step followed by chromic acid etch. The other alternative is to mold the first part with noncatalyzed plastic materials and expose the molded part to an adhesion promotion process and catalyze. The second part is then molded, as in the first case. These parts are placed in an electroless plating bath for circuitization. A high rate of growth is expected for MIDs, with the automotive market being the most promising application area.
REFERENCES
1. W. A. Alpaugh and J. M. McCreary, IPC-TP-108, Fall Meeting, 1976. 2. R. R. Tummala and S. Ahmed, Overview of Packaging for the IBM Enterprise System 9000 Based on the Glass-Ceramic Copper/Thin Film Thermal Conduction Module, IEEE Trans. on Comp., Hybrids and Mfg. Tech., Vol. 14, No. 4, Dec. 1991, pp. 426 431. 3. L. E. Thomas, et al., Second-Level Packaging for the High End ES/9000 Processors, IBM J. of Research & Development. 4. H. Murano and T. Watari, Packaging Technology for the NEC SX-3 Supercomputers, IEEE Trans. on Comp., Hybrids and Mfg. Tech., Vol. 15, No. 4, Aug. 1992, pp. 411 417. 5. A. Takahashi, et al., High Density Multilayer Printed Circuit Board for HITAC M-880, op. cit., pp. 418 425. 6. Clyde F. Coombs, Jr. (ed.), Printed Circuits Handbook, 3d ed., McGraw-Hill, New York, 1986, Chap. 13. 7. U.S. Patent 2,938,805, 1960. 8. U.S. Patent 3,628,999, Dec. 1971. 9. U.S. Patent 3,799,802, Mar. 1974. 10. U.S. Patent 3,799,816, Mar. 1974. 11. U.S. Patent 3,600,330, Aug. 1971. 12. Japanese Patent 43-16929, July 1968. 13. Japanese Patent 58-6319, Feb. 1983. 14. H. Steffen, Additive Process, Ruwel Werke GmbH, private communication. 15. K. Minten and J. Toth, PWB Interconnect Strategy Using a Full Build Electroless Plating System: Part I, PC World Conference V, Paper No. b-52, Glasgow, Scotland, June 1990. 16. K. Minten, J. Seigo, and J. Cisson, Part 2: Etch Characteristics, Circuit World, Vol. 18, No. 4,Aug 1992, pp. 5 12. 17. K. Minten and J. Cisson, Part 3: Characterization of a Semi-Additive Naked Palladium Catalyst, Circuit World, Vol. 19, No. 2, Jan. 1993, pp. 4 13. 18. K. Minten, K. Kitchens, and J. Cisson, Part 4: The Future of FBE Process, private communication. 19. N. Ohtake, Electronics Technology (Japanese), 27(7), June 1985, pp. 55 59. 20. N. Ohtake, New Printed Wiring Boards by a Partly Additive Process, PC World Conference IV, Tokyo, Paper No. 44, June 1987. 21. S. Imabayashi, et al., Partly-Additive Process for Manufacturing High-Density Printed Wiring Boards, IEEE Trans. 0569-5503/92/0000-1053, 1992. 22. H. Akaboshi, A New Fully Additive Fabrication Process for Printed Wiring Boards, IEEE Trans. on Comp., Hybrids and Mfg. Tech., Vol. CHMT-9, No. 2, June 1986. 23. R. Enomoto, et al., Advanced Full-Additive Printed Wiring Boards Using Heat Resistant Adhesive, PC World Conf V, Paper No. B6-1, Glasgow, Scotland, June 1990. 24. K. Ikai, Full Additive Boards, Electronic Materials (Japanese), Oct. 1993, pp. 58 63.
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