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FIGURE 54.2 Circuitry made up of gates and flip-flops, redrawn to show that it can be represented as a bank of memory elements and a combinatorial circuit.
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its derivatives). These tests could be shifted into the circuit and applied, and the results shifted out. This takes a lot of bookkeeping, but computers are good at that. By using the LSSD discipline, IBM could verify that its designs would be completely testable, and those tests could be created by a computer program. Other companies such as Sperry Univac, Amdahl, Hitachi, etc., had similar proprietary structured approaches. Most smaller, nonintegrated companies were not able to participate in structured DFT that is, until nonproprietary industry standards came into play.
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In the closing years of the 1980s, it became apparent that some sort of structured testability technology had to become accessible to the electronics industry at large. A small group of
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European companies led by Philips formed the Joint European Test Action Group (JETAG) and began work on a testability standard. The effort quickly attracted the notice of North American companies, giving rise to the JTAG standard. As the proposal took shape, it was turned over to the IEEE, which ultimately produced IEEE Standard 1149.1-1990, Standard Test Access Port and Boundary-Scan Architecture,3 in 1990.* Soon after 1149.1 came into being, a companion effort created IEEE Std 1149.4-1999, Standard for a Mixed-Signal Test Bus.4 A complete coverage of these standards is beyond the scope of this chapter (see Ref. 5), so a brief summary is given here for an overview.
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IEEE 1149.1, Boundary-Scan for Digital Circuits The IEEE 1149.1 standard is a design discipline for digital ICs. It is a set of rules impressed primarily on the I/O structures of a device that allow two modes of operation, normal mode and test mode. In normal mode, the device performs its intended function. In test mode, the device obeys a protocol that has mandatory, optional, and customizable elements. The mandatory elements must exist, with the others being left as design options. The principle mandatory element of interest is a test mode dedicated to external test or EXTEST. When an 1149.1compliant device is in EXTEST mode, its I/O pins are divorced from their normal operation and all internal functions of the device. Instead, the inputs become observation resources and the outputs become control resources for test purposes. These resources are under control of the 1149.1 serial scan protocol. One can think of the I/O pins of the device being connected to shift register cells; states can be shifted in that will finally appear on all output pins (control) and the states of all input pins can be captured and shifted out (observe). This gives 1149.1cognizant software a powerful tool for controlling and/or observing board-level node states. Figure 54.3 shows a simplified overview of the architecture. Boundary register cells interposed between the IC pins and the internal logic surround the normal content of the IC called the mission logic. A small state machine called the test access port (TAP) is used to control the test functions. Four mandatory test pins (test clock [TCK], test mode select [TMS], test data in [TDI], and test data out [TDO]) give standardized access to the test functions. All 1149.1 devices have a 1-bit BYPASS register used to bypass the (much longer) boundary register if it is not needed in a given testing activity. Figure 54.3 also shows an optional IDCODE register that can be shifted out to uniquely identify the IC, its manufacturer, and its revision. It is intended that collections of ICs (called chains, as shown in Fig. 54.4) with 1149.1 be connected TDO-to-TDI so that they may form a long, shiftable register structure.The primary use for the 1149.1 EXTEST capability is to conduct board-level tests for shorts and opens. This is an example of how resources included in an IC design may be used to help with the testing problem at other levels in the manufacturing process. Briefly, interconnections between ICs are tested as follows. Consider the circuitry in Fig. 54.5. Some circuit nodes (also known as nets or traces) are accessible with a bed of nails and some are not. (To avoid clutter, the TCK and TMS signals are not shown.) Boundary scan can be used to test all the nodes; those with nails can be tested by coordinating nails with boundary scan resources and those without nails are tested solely with boundary scan.
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* An IEEE standard has as a suffix the year of its creation or last update. A standard must be updated and/or reaffirmed every 5 years. Up to two supplements to a standard may be issued within the 5-year cycle. Users of a standard should keep up to date with it. Bidirectional signal pins can both observe and control the nodes to which they are connected. An optional fifth pin called Test Reset (TRST*) is an asynchronous active low reset for the 1149.1 circuitry. Because any TAP can be reset by five clock pulses to TCK while TMS is held high, TRST* is not actually needed for resetting an 1149.1 device. It is often included as a fail-safe measure with a board-level pull-down resistor providing a constant reset to the TAP. Many 1149.1-compliant ICs do not include the TRST* pin because the extra pin required may be too costly.
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