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than having its identity masked by interactions with other devices. This is a major differentiation from functional testing. Faults typically can be resolved to two categories of defects: failed ICs or solder opens on I/O/power pins. Another major differentiator is the ease indeed, automation of test programming that is possible with digital in-circuit testing. Tests for ICs can be prepared as if the ICs were standing alone,* stored in a library, and recalled from the library when needed. Modern digital in-circuit testers may have library tests for tens of thousands of devices. For custom, one-of-a-kind ICs for which a library test may not exist (e.g., ASICs), it is still substantially easier to create a test for just the one device than it is for a collection of ICs. 55.5.3 Manufacturing Defect Analyzer (MDA) A manufacturing defect analyzer (MDA) is essentially a very low-end analog in-circuit tester. One way it maintains low equipment cost is by not having power supplies to power up a board. Another cost savings comes by having only rudimentary programming and operating software. Some amount of test accuracy and yield must be traded for these savings. 55.5.4 General-Purpose In-Circuit Tester The workhorse of the electronics industry is the general-purpose in-circuit tester that merges support for analog and digital in-circuit tests. An example of a widely used system is shown in Fig. 55.10. It contains power supplies for powering boards and often contains sophisticated
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* This assumes that the IC does not have any topological constraints on its I/O pins, such as having an input pin connected directly to ground or an output pin fed back to an input pin. In such cases, the prepared test may be incompatible with these constraints and may only be used after incompatible segments of the test are deleted, reducing fault coverage.
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FIGURE 55.10 Example of a commercial in-circuit test head and operator terminal, with a printed circuit board mounted in the testing position on top of the bed-of-nails fixture.
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analog in-circuit programming tools and extensive libraries of digital tests. The typical test and repair flow for this tester is shown in Fig. 55.11. Note the early exit to repair for boards that fail shorts testing. This avoids applying power to boards that contain shorts because these may present hazards to the board and human operator, plus they also confuse the diagnosis of faults later in testing.
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FIGURE 55.11 Typical test and repair flow for an in-circuit tester.
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Combinational Tester In situations where a manufacturing line has a variety of technologies in production, a need may exist for both functional and in-circuit testing. Thus, hybrid functional/in-circuit testers (commonly called combinational testers) exist. These machines give test engineers a full
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complement of tools to address testing problems. They also allow one-stop testing, where manufacturing defects and functional performance faults can be detected at one site in the production flow. A combinational tester utilizes a bed of nails to perform in-circuit analog and digital tests. It may also utilize edge connector access to perform functional tests. In some cases these approaches are hybridized by constructing a two-stage bed-of-nails fixture that has two lengths of nails used in the bed, and a platen that has two stations of depression during operation. The first station is full depression, which brings all nails into contact with the circuit board for standard in-circuit access. The second station is partial depression, where only the longer nails still contact the board, perhaps at the board edge, for functional testing. The removal of the shorter nails removes the electrical loading they present to internal circuit nodes and allows the board to operate in a more natural environment.
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Alternative tests use radically different approaches to specifically address the resolution of defects. These may be needed to address blind spots in traditional electrical test methodologies. Two specific examples of defects that are difficult to resolve by conventional tests are given here. First, consider a board with a large number of bypass capacitors. All of these capacitors are connected between power and ground so their parallel capacitances are summed. Using an analog in-circuit test, it is possible to test for this summed capacitance. However, if one capacitor is missing or tombstoned, the tester most likely will not notice because the resulting decrement in capacitance will likely fall well within the summed tolerances of the summed capacitances. The performance of the board at higher operating frequencies may be adversely affected, however, due to a loss of noise immunity. This could be detected (possibly) by a performance test. However, if this performance test failed, it could be very difficult to resolve which capacitor was missing. One non-traditional way to test for this problem is to use human visual inspection to look for missing capacitors. This may not find solder opens, however. Another approach would be to use an automated x-ray laminographic tester to check for the existence and solder integrity of each capacitor. Even the orientation of polarized capacitors can be verified. (See Chap. 53 for a discussion of x-ray inspection.) Second, consider again the open solder problem on a digital device input. This defect may manifest itself as improper device behavior, but it would be wrong to replace the device (which would also fix the solder open) because the device is not at fault. Digital in-circuit testing has trouble resolving solder opens on input pins from bad devices.* Final resolution can be obtained either by visual inspection or by using a handheld probe to see if board signals reach IC legs, but this is becoming increasingly difficult as packaging dimensions continue to shrink (e.g., TAB) and newer attachment technologies (e.g., ball grid arrays) are used that prohibit visual inspection or probing altogether. An alternative approach to the open solder problem uses a capacitive coupling technique to look for opens. The technique exploits the fact that many ICs have a leadframe that forms the conductive path from the legs of the device to the die bond wire pads. Using the bed of nails, all but one node attached to the IC can be grounded (this is an unpowered technique) and a small AC signal can be applied to the node that remains. An insulated metal plate pressed against the top of the IC forms the top plate of a capacitor and the stimulated IC leg and lead frame conductor form the bottom plate.
* Ignore for the moment the possibility of using boundary scan to solve this problem, which is discussed in Chap. 54.
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