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The low-end PIC microcontroller devices have ve register bank address bits for up to 32 unique le register addresses in each bank. Up to four register banks can be available in a low-end PIC microcontroller, with the rst 16 addresses of each bank being common throughout the banks and the second 16 addresses being unique to the bank. This is shown in Fig. B.1. Using this scheme, low-end PIC microcontrollers have anywhere from 25 to 73 unique le registers available to an application (see Table B.8). There are a few things to note with low-end register addressing:
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1 The OPTION and TRIS registers can be written to only by the option and tris
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instructions, respectively.
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PIC MICROCONTROLLER SUMMARY
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Bank 0 Addr - Reg 00 - INDF 01 - TMR0 02 - PCL 03 - STATUS 04 - FSR 05 - PORTA* 06 - PORTB 07 - PORTC 08-0F Shared File Regs 10-1F Bank 0 File Regs
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Bank 1 Addr - Reg 20 - INDF 21 - TMR0 22 - PCL 23 - STATUS 24 - FSR 25 - PORTA* 26 - PORTB 27 - PORTC 28-2F Shared File Regs 30-3F Bank 1 File Regs
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Bank 2 Addr - Reg 40 - INDF 41 - TMR0 42 - PCL 43 - STATUS 44 - FSR 45 - PORTA* 46 - PORTB 47 - PORTC 28-2F Shared File Regs 50-4F Bank 2 File Regs
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Bank 3 Addr - Reg 60 - INDF 61 - TMR0 62 - PCL 63 - STATUS 64 - FSR 65 - PORTA* 66 - PORTB 67 - PORTC 68-8F Shared File Regs 70-7F Bank 3 File Regs Bank Unique Registers Shared Registers
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* - OSCCAL may take place of PORTA in PICMicros with Internal Oscillators OPTION - Accessed via option Instruction TRIS# - Accessed via TRIS PORT# Instruction
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Figure B.1 The Low-End PIC microcontroller processor architecture is limited to four banks of up to 32-byte-wide registers.
2 If the device has a built-in oscillator, the OSCCAL register is located in address 5,
which is normally the PORTA address.
3 The STATUS and OPTION registers are always the same for low-end devices. 4 The low-end PIC microcontroller FSR register can never equal zero.
MID-RANGE PIC MICROCONTROLLER REGISTERS
If you look at the different mid-range PIC microcontroller devices, you will see that there is a great diversity in the register sets available to the various part numbers. This is quite a bit different from the other three PIC MCU families, in which the registers can be found at speci c locations across the family. The diversity in the mid-range PIC microcontroller family is caused by the myriad of different features that have been released over the past few years, along with the number of different pin counts of the various devices. Despite this diversity, there are some standard addresses (listed in Table B.9) that you can always count on with mid-range PIC microcontrollers. I always start with the block of registers in bank 0 and bank 1 listed in the table and then add to them the features that are built into the speci c PIC microcontroller part number. From these basic addresses, peripheral I/O registers (discussed below) are added to the register banks, with le registers starting at either offset 0x0C or 0x20. For most modern mid-range PIC microcontrollers, the le registers start at address 0x20 of the bank. The speci c part number datasheets will have to be checked to nd where the le registers that are shared across the banks are located.
APPENDIX B
TABLE B.8 ADDRESS
LOW-END PIC MICROCONTROLLER REGISTER DEFINITIONS REGISTER BITS BIT FUNCTION
0x003
STATUS
GPWUF in PIC12C5xx and PIC16C505, when set, reset from sleep on pin change; when set, power up or _MCLR reset; in other devices, bit 7 is unused. PA1 PA0 select the page to execute out of: 00 page 0 (0x0000 0x01FF) 01 page 1 (0x0200 0x03FF) 10 page 2 (0x0400 0x05FF) 11 page 3 (0x0600 0x07FF) _TO set after power up and clrwdt and sleep instructions. _PD set after power up and clrwdt instruction; reset after sleep instruction. Z set if the 8-bit result is equal to zero. DC set for low-order nybble carry after addition or subtraction instruction. C set for carry after addition or subtraction instruction. _GPWU in PIC12C5xx or PIC16C505, reset to enable wake-up on pin change; in other devices, bit 7 is unused. _GPPU in PIC12C5xx or PIC16C505, enable pin pull-ups; in other devices, bit 6 is unused. T0CS TMR0 clock source select; when set, T0CKI pin is source; when reset, instruction clock. T0SE TMR0 edge select; when reset, increment TMR0 on rising edge; when set, increment TMR0 on falling edge. PSA prescaler assignment bit; when set, the prescaler is assigned to the watchdog timer, else TMR0. PS2 PS0 prescaler rate select bits Bit TMR0 rate: 111 256:1 110 128:1 101 64:1 100 32:1 011 16:1 010 8:1 001 4:1 000 2:1
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