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where P1P2, and so on are the parity symbols selected by the encoding rules from the symbol alphabet A, B, C, and D. This process is illustrated in Fig. 11.1. At the decoder, these are the only words that are recognized as being legitimate and can be decoded. The other possible codewords not formed by the rules but which may be formed by transmission errors will be detected as errors and corrected. It will be observed that a codeword consists of 6 bits, and one or more of these in error will result in a symbol error. The R-S code is capable of correcting this symbol error, which in this simple illustration means that a burst of up to 6 bit errors can be corrected. R-S codes do not provide efficient error correction where the errors are randomly distributed as distinct from occurring in bursts (Taub and Schilling, 1986). To deal with this situation, codes may be joined together or concatenated, one providing for random error correction and one for burst error correction. Concatenated codes are described in Sec. 11.6. It should be noted that although the encoder and decoder in R-S codes operate at the symbol level, the signal may be transmitted as a bit stream, but it is also suitable for transmission with multilevel modulation, the levels being determined by the symbols. The code rate is rc K/N, and the code is denoted by (N, K). In practice, it is often the case that the symbols are bytes consisting of 8 bits; then q 28 256, and N q 1 255. With t 8, a NASA-standard (255, 239) R-S code results. Shortened R-S codes employ values N N l and K K l and are denoted as (N , K ). For example, DirecTV (see Chap. 16) utilizes a shortened R-S code for which l 109, and digital video broadcast (DVB) utilizes one for which l 51 (Mead, 2000). These codes are designed to correct up to t 8 symbol errors. 11.4 Convolution Codes Convolution codes are also linear codes. A convolution encoder consists of a shift register which provides temporary storage and a shifting operation for the input bits and exclusive-OR logic circuits which generate the coded output from the bits currently held in the shift register. In general, k data bits may be shifted into the register at once, and n code bits generated. In practice, it is often the case that k 1 and n 2, giving rise to a rate 1/2 code. A rate 1/2 encoder is illustrated in Fig. 11.2, and this will be used to explain the encoding operation. Initially, the shift register holds all binary 0s. The input data bits are fed in continuously at a bit rate Rb, and the shift register is clocked at this rate. As the input moves through the register, the rightmost bit is shifted out so that there are always 3 bits held in the register. At the end of the message, three binary 0s are attached, to return the shift register
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U1 Input data S1 S2 S3 U2 Encoded output
A rate 1/2 convolutional encoder.
to its initial condition. The commutator at the output is switched at twice the input bit rate so that two output bits are generated for each input bit shifted in. At any one time the register holds 3 bits which form the inputs to the exclusive-OR circuits. Figure 11.3 is a tree diagram showing the changes in the shift register as input is moved in, with the corresponding output shown in parentheses. At the initial condition, the register stores 000, and the output is 00. If the first message bit in is a 1, the lower branch is followed, and the output is seen to be 11. Continuing with this example, suppose that the next three input bits are 001; then the corresponding output is 01 11 11. In other words, for an input 1001 (shown shaded in Fig. 11.3), the output, including the initial condition (enclosed here in brackets), is [00] 11 01 11 11. From this example it will be seen that any given input bit contributes, for as long as it remains in the shift register, to the encoded word. The number of stages in the register gives the constraint length of the encoder. Denoting the constraint length by m, the encoder is specified by (n, k, m). The example shows a (2, 1, 3) encoder. Encoders are optimized through computer simulation. At the receiver, the tree diagram for the encoder is known. Decoding proceeds in the reverse manner. If, for example, [00] 11 01 11 11 is received, the tree is searched for the matching branches, from which the input can be deduced. Suppose, however, that an error occurs in transmission, changing the received word to [00] 01 01 11 11; i.e., the error is in the first bit following the initial condition. The receiver decoder expects either a 00 or a 11 to follow the initial 00; therefore, it has to make the assumption that an error has occurred. If it assumes that 00 was intended, it will follow the upper branch, but now a further difficulty arises. The next possible pair is 00 or 11, neither of which matches the received code word. On the other hand, if it assumes that 11 was
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