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codes, (known as Turbo Product codes or TPCs, see Comtech, 2002). However the more common arrangement is to use parallel concatenation using convolution encoders. Because of the continuous nature of convolution coding, data and code sequences rather than words are involved. The convolution encoders shown in Fig. 11.11 (Burr, 2001) are recursive convolution encoders. They differ from the convolution encoder of Fig. 11.2 in that feedback is employed. (This recursive feedback is part of the encoding process and is quite separate from the iterative feedback to be described shortly, which gives turbo codes their name). It can be shown that the recursive feedback (see Burr, 2001) assists in maintaining a large minimum Hamming distance (see Sec. 11.2) for code sequences. Another difference between the encoders of Fig. 11.11 and that of Fig. 11.2 is that the data sequence is fed directly to the multiplexer of Fig. 11.11, making the output systematic (see Sec. 11.2). Parity-1 bits are generated directly from the data bits and parity-2 bits from the interleaved data bits, so that two independent streams of parity bits are generated. Interleaving as described in Sec. 11.5, was used there as a means of combating bursty errors. With turbo encoding the purpose of interleaving is different, it is used to provide independent parity bits for the same input. A number of different methods of interleaving are available, and the design of the interleaver is a crucial aspect of turbo code design. The output coded sequence is data, parity-1, parity-2. Since each encoder generates a parity bit for every data bit the code rate is 1/3. This is relatively low but can be increased by puncturing, as described in Sec. 11.4 and shown in Fig. 11.11. For example, one parity bit might be discarded in turn from each of the encoders, resulting in a 1/2 code rate. Other rates are possible with puncturing. If puncturing is used with the encoder, dummy bits are inserted at the decoder to replace
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A turbo encoder with puncturing. The symbol indicates an interleaver, and the { symbol indicates modulo-2 addition. (Courtesy of A Burr and the IEEE.)
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those discarded. The dummy bit level is set midway between the binary 1 and 0 levels, so they do not affect the decoding process. The block schematic for the decoder is shown in Fig. 11.12 (Burr, 2001). The demultiplexer provides outputs for the data sequence and parity-1 and parity-2 sequences. These outputs are soft, meaning that some measure of the bit level is used rather than a hard decision output of binary 1 or 0. For example, assuming a threshold decision level of 0.5V, the demultiplexer output might be 0.9V, 0.7V 0.1V, 0.2V, 0.9V, 0.65V, 0.3V, suggesting a hard decision binary sequence of 1 1 0 0 1 1 0. However the hard decision output does not make use of the likelihood of the hard decision being correct. The 0.9V level is obviously more likely to be a binary1 than the 0.65V level. A statistical measure termed the log-likelihood ratio (LLR) is most commonly used. For a given received value r, let p(1/r) represent the probability that a 1 was transmitted, and p(0/r) the probability that a 0 was transmitted. The log likelihood ratio is defined as LLR loge a p(1>r) p(0>r) b (11.23)
Where the transmission of 1s and 0s are equiprobable, (the probability of either a 1 or 0 occurring being 1/2 , rather like the probability of heads or tails of a the toss of a fair coin) the LLR becomes: LLR loge a p(r>1) p(r>0) b loge p(r/0)
(11.24)
loge p(r/1)
2 1 0
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