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coding is employed, the distinction between Pe and BER becomes important. Pe is still determined by conditions at the input, but the error control will, if properly implemented, make the probability of bit error at the output (the BER) less than that at the input. Error control coding applies only to digital signals, and in most cases the signal is in binary form, where the message symbols are bits, or logic 1s and 0s. Encoding refers to the process of adding coding bits to the uncoded bit stream, and decoding refers to the process of recovering the original (uncoded) bit stream from the coded bit stream. Both processes are usually combined in one unit termed a codec. 11.2 Linear Block Codes A block code requires that the message stream be partitioned into blocks of bits (considering only binary messages at this stage). Let each block contain k bits, and let these k bits define a dataword. The number of datawords is 2k. There is no redundancy in the system, meaning that even a single bit error in transmission would convert one dataword into another, which of course would constitute an error. The datawords can be encoded into codewords which consist of n bits, where the additional n k bits are derived from the message bits but are not part of the message. The number of possible codewords is 2n, but only 2k of these will contain datawords, and these are the ones that are transmitted. It follows that the rest of the codewords are redundant, but only in the sense that they do not contribute to the message. (The n k additional bits are referred to as parity check bits). If errors occur in transmission, there is high probability that they will convert the permissible codewords into one or another of the redundant words that the decoder at the receiver is designed to recognize as an error. It will be noted that the term high probability is used. There is always the possibility, however remote, that enough errors occur to transform a transmitted codeword into another legitimate codeword in error. The code rate rc is defined as the ratio of dataword bits to codeword bits (note that although it is called a rate, it is not a rate in bits per second) rc k n (11.1)
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The code is denoted by (n, k) for example a code which converts a 4-bit dataword into a 7 bit codeword would be a (7, 4) code. A repetition code illustrates some of the general properties of block codes. In a repetition code, each bit is considered to be a dataword, in effect, k 1. For n-redundancy encoding, the output of the encoder is n bits, identical to the input bit. As an example, consider the situation
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when n 3. A binary 1 at the input to the encoder results in a 111 codeword at the output, and a binary 0 at the input results in a 000 codeword at the output. At the receiver, the logic circuits in the decoder produce a 1 when 111 is present at the input and a 0 when 000 is present. It is assumed that synchronization is maintained between encoder and decoder. If a codeword other than 111 or 000 is received, the decoder detects an error and can request a retransmission (ARQ). FEC can take place on the basis of a majority vote. In this case, the logic circuits in the decoder are designed to produce a 1 at the output whenever two or three 1s occur in the received codeword (codewords 111, 101, 011, and 110) and a 0 whenever two or three 0s appear in the codeword (codewords 000, 001, 010, and 100). An odd number of repeats is used to avoid a tied vote. Errors can still get through if the noise results in two or three successive errors in a codeword. For example, if the noise changes a 111 into a 000 or a 000 into a 111, the output will be in error whether error detection or FEC is used. If two errors occur in a codeword, then the majority vote method for FEC will result in an error. However, the probability of two or three consecutive errors occurring is very much less than the probability of a single error. This assumes that the bit energy stays the same, an aspect that is discussed in Sec. 11.7. Codes that are more efficient than repetitive encoding are generally used in practice. As a matter of definition, a code is termed linear when any linear combination of two codewords is also a codeword. For binary codewords in particular, the linear operation encountered is modulo-2 addition. The rules for modulo-2 addition are: 0 0 0 0 1 1 1 0 1 1 1 0
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Modulo-2 addition is easily implemented in hardware using the exclusiveOR (XOR) digital circuit, which is one of its main advantages. All codes encountered in practice are linear, which has a bearing on the theoretical development (see Proakis and Salehi, 1994). To illustrate this further consider the eight possible datawords formed from a 3-bit sequence. One parity bit will be attached to each dataword as shown in the Table 11.1. The parity bits are selected to provide even parity, that is, the number of 1s in any codeword is even (including the all-zero codeword). The parity bits are found by performing a modulo-2 addition on the dataword. With even parity it is seen that the bits in the codeword modulo-2 sum to zero. It would be possible to use odd parity where the parity bit is chosen so that the modulo-2 sum of the codeword is 1, however this would exclude the all-zero codeword. A linear code must include the allzero codeword, and hence even parity is used.
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